Issued Patents All Time
Showing 26–50 of 107 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9806170 | Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI | George R. Mulfinger, Ryan Sporer, Rick Carter, Hans-Jürgen Thees, Jan Höntschel | 2017-10-31 |
| 9793294 | Junction formation with reduced Ceff for 22nm FDSOI devices | Hans-Juergen Thees | 2017-10-17 |
| 9735174 | FDSOI—capacitor | Jan Hoentschel, Hans-Peter Moll | 2017-08-15 |
| 9673210 | Semiconductor structure including a nonvolatile memory cell having a charge trapping layer and method for the formation thereof | Hans-Juergen Thees, Joerg Schmid | 2017-06-06 |
| 9666589 | FinFET based flash memory cell | Juergen Faul | 2017-05-30 |
| 9634088 | Junction formation with reduced CEFF for 22NM FDSOI devices | Hans-Juergen Thees | 2017-04-25 |
| 9634017 | Semiconductor structure including a nonvolatile memory cell and method for the formation thereof | Hans-Juergen Thees | 2017-04-25 |
| 9608110 | Methods of forming a semiconductor circuit element and semiconductor circuit element | Carsten Grass | 2017-03-28 |
| 9608003 | Integrated circuit product with bulk and SOI semiconductor devices | Hans-Peter Moll, Jan Hoentschel | 2017-03-28 |
| 9564521 | Semiconductor device comprising ferroelectric elements and fast high-K metal gate transistors | Till Schloesser | 2017-02-07 |
| 9553046 | E-fuse in SOI configuration | Jan Hoentschel, Hans-Peter Moll | 2017-01-24 |
| 9553030 | Method of manufacturing P-channel FET device with SiGe channel | Hans-Peter Moll | 2017-01-24 |
| 9502564 | Fully depleted device with buried insulating layer in channel region | Hans-Peter Moll, Jan Hoentschel | 2016-11-22 |
| 9484457 | Vertical floating body storage transistors formed in bulk devices and having buried sense and word lines | Till Schloesser | 2016-11-01 |
| 9466685 | Semiconductor structure including at least one electrically conductive pillar, semiconductor structure including a contact contacting an outer layer of an electrically conductive structure and method for the formation thereof | Hans-Peter Moll, Thorsten Kammler | 2016-10-11 |
| 9443871 | Cointegration of bulk and SOI semiconductor devices | Hans-Peter Moll, Jan Hoentschel | 2016-09-13 |
| 9425189 | Compact FDSOI device with Bulex contact extending through buried insulating layer adjacent gate structure for back-bias | Hans-Peter Moll | 2016-08-23 |
| 9391156 | Embedded capacitor | Hans-Peter Moll, Jan Hoentschel | 2016-07-12 |
| 9385232 | FD devices in advanced semiconductor techniques | Hans-Peter Moll, Jan Hoentschel | 2016-07-05 |
| 9349842 | Methods of forming semiconductor devices comprising ferroelectric elements and fast high-K metal gate transistors | Till Schloesser | 2016-05-24 |
| 9337045 | Methods of forming a semiconductor circuit element and semiconductor circuit element | Carsten Grass | 2016-05-10 |
| 9324854 | Semiconductor device comprising self-aligned contact elements and a replacement gate electrode structure | Till Schloesser, Frank Jakubowski | 2016-04-26 |
| 9214463 | Methods of forming metal silicide regions on a semiconductor device | Hans-Juergen Thees | 2015-12-15 |
| 9177871 | Balancing asymmetric spacers | Joachim Patzer, Bastian Haussdoerfer | 2015-11-03 |
| 9136175 | Methods for fabricating integrated circuits | Andy Wei, Erik Geiss | 2015-09-15 |