Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12159848 | Method of forming a sensor device having moisture sensitive dielectric layer with integrally formed projections | Ee Jan Khor, Juan Boon Tan | 2024-12-03 |
| 12102020 | Semiconductor memory devices having an electrode with an extension | Jianxun Sun, Juan Boon Tan | 2024-09-24 |
| 12094763 | Metal-insulator-metal capacitor (MIMCAP) and methods of forming the same | Kwang Yew, Juan Boon Tan | 2024-09-17 |
| 12034039 | Three electrode capacitor structure using spaced conductive pillars | EeJan Khor, Juan Boon Tan | 2024-07-09 |
| 12009326 | SRAM bit cells with three-dimensional integration | Hari Balan, Juan Boon Tan, Wanbing Yi | 2024-06-11 |
| 11855019 | Method of forming a sensor device | Ee Jan Khor, Juan Boon Tan | 2023-12-26 |
| 11646279 | Contact pad structures and methods for fabricating contact pad structures | Xiaodong Li, Juan Boon Tan | 2023-05-09 |
| 11444045 | Bonding structures of semiconductor devices | Juan Boon Tan, Xiaodong Li, Kai Chong Chan, Ranjan Rajoo | 2022-09-13 |
| 11244915 | Bond pads of semiconductor devices | Juan Boon Tan, Chee Kong Leong, Ranjan Rajoo, Xuesong Rao, Xiaodong Li | 2022-02-08 |
| 11217496 | Test pad with crack stop protection | Juan Boon Tan, Wanbing Yi | 2022-01-04 |
| 10892239 | Bond pad reliability of semiconductor devices | Juan Boon Tan, Ian Melville | 2021-01-12 |
| 10658316 | Bond pad reliability of semiconductor devices | Xiaodong Li, Juan Boon Tan | 2020-05-19 |
| 10170437 | Via disguise to protect the security product from delayering and graphic design system (GDS) hacking and method for producing the same | Juan Boon Tan, Sung Mun Jung, Wenhu Liu, Ee Jan Khor | 2019-01-01 |
| 10170439 | Chamfering for stress reduction on passivation layer | Ee Jan Khor, Juan Boon Tan, Wanbing Yi, Qian Chen, Suleni Tunggal Mulia +1 more | 2019-01-01 |
| 8183127 | Method for bonding wafers to produce stacked integrated circuits | Robert Patti, Sangki Hong | 2012-05-22 |
| 7750488 | Method for bonding wafers to produce stacked integrated circuits | Robert Patti, Sangki Hong | 2010-07-06 |
| 6548413 | Method to reduce microloading in metal etching | Paul Ho, Thomas Schulue, Raymond Joy, Wai Lok Lee, Ba Tuan Pham +1 more | 2003-04-15 |
| 6380087 | CMP process utilizing dummy plugs in damascene process | Subhash Gupta, Mei Sheng Zhou | 2002-04-30 |
| 6274499 | Method to avoid copper contamination during copper etching and CMP | Subhash Gupta, Paul Ho, Mei Sheng Zhou | 2001-08-14 |