Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
RP

Robert Patti — 22 Patents

TSTezzaron Semiconductor: 5 patents #1 of 9Top 15%
PHP-Chip Ip Holdings: 2 patents #7 of 11Top 65%
TSTachyon Semiconductor: 2 patents #1 of 3Top 35%
TEThe Ensign-Bickford: 2 patents #33 of 81Top 45%
PHPharmaseq: 1 patents #4 of 21Top 20%
University of California: 1 patents #8,022 of 18,278Top 45%
Warrenville, IL: #2 of 171 inventorsTop 2%
Illinois: #3,329 of 84,256 inventorsTop 4%
Overall (All Time): #189,202 of 4,157,543Top 5%
22 Patents All Time
Robert Patti has been granted 22 US patents while listed as an inventor at Tezzaron Semiconductor. The first was granted in 1999 and the most recent in December 2024. Robert Patti ranks #189,202 of 4,157,543 US inventors in our database (top 4.6%). Patent records list Robert Patti in Warrenville, IL, US.

Issued Patents All Time

Showing 1–22 of 22 patents

Patent #TitleCo-InventorsDate
12166528 All optical identification and sensor system with power on discovery Wlodek Mandecki, Efrain Rodriguez, Ioannis Kymissis 2024-12-10
11483072 All optical identification and sensor system with power on discovery Wlodek Mandecki, Efrain Rodriguez, Ioannis Kymissis 2022-10-25
11133866 All optical identification and sensor system with power on discovery Wlodek Mandecki, Efrain Rodriguez, Ioannis Kymissis 2021-09-28
10859776 Optical-electrical interposers Sung-Joo Ben Yoo 2020-12-08
8222121 Fiducial scheme adapted for stacked integrated circuits Sangki Hong, Chockalingam Ramasamy 2012-07-17
8183127 Method for bonding wafers to produce stacked integrated circuits Sangki Hong, Ramasamy Chockalingam 2012-05-22
7898095 Fiducial scheme adapted for stacked integrated circuits Sangki Hong, Chockalingam Ramasamy 2011-03-01
7750488 Method for bonding wafers to produce stacked integrated circuits Sangki Hong, Ramasamy Chockalingam 2010-07-06
7159047 Network with programmable interconnect nodes adapted to large integrated circuits Mark D. Klecka, Kamal Khadiri, Derrick Wilson, Lee Hoyman, Bruce Tyda 2007-01-02
6838774 Interlocking conductor method for bonding wafers to produce stacked integrated circuits 2005-01-04
6785860 Error-correcting code adapted for memories that store multiple bits per storage cell 2004-08-31
6642081 Interlocking conductor method for bonding wafers to produce stacked integrated circuits 2003-11-04
6469945 Dynamically configurated storage array with improved data access Mark Francis Hilbert 2002-10-22
6400612 Memory based on a four-transistor storage cell 2002-06-04
6373767 Memory that stores multiple bits per storage cell 2002-04-16
6300660 Bipolar transistor that can be fabricated in CMOS 2001-10-09
6271587 Connection arrangement for enbaling the use of identical chips in 3-dimensional stacks of chips requiring address specific to each chip 2001-08-07
6268775 Dual capacitor oscillator circuit 2001-07-31
6236602 Dynamic configuration of storage arrays 2001-05-22
6154392 Four-terminal EEPROM cell for storing an analog voltage and memory system using the same to store multiple bits per EEPROM cell 2000-11-28
6141261 DRAM that stores multiple bits per storage cell 2000-10-31
5912428 Electronic circuitry for timing and delay circuits 1999-06-15