Issued Patents All Time
Showing 26–50 of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7723805 | Electronic device including a fin-type transistor structure and a process for forming the electronic device | Marius Orlowski | 2010-05-25 |
| 7718485 | Interlayer dielectric under stress for an integrated circuit | Jon D. Cheel | 2010-05-18 |
| 7709303 | Process for forming an electronic device including a fin-type structure | Leo Mathew, Byoung W. Min | 2010-05-04 |
| 7684264 | Memory system with RAM array and redundant RAM memory cells having a different designed cell circuit topology than cells of non redundant RAM array | Bradford Lawrence Hunter, Andrew C. Russell, Shayan Zhang | 2010-03-23 |
| 7608898 | One transistor DRAM cell structure | Brian A. Winstead | 2009-10-27 |
| 7609541 | Memory cells with lower power consumption during a write operation | Glenn C. Abeln, Jack M. Higman | 2009-10-27 |
| 7542369 | Integrated circuit having a memory with low voltage read/write operation | Prashant U. Kenkare, Andrew C. Russell, David R. Bearden, Troy L. Cooper, Shayan Zhang | 2009-06-02 |
| 7517741 | Single transistor memory cell with reduced recombination rates | Marius Orlowski | 2009-04-14 |
| 7488635 | Semiconductor structure with reduced gate doping and methods for forming thereof | Brian A. Winstead, Sinan Goktepeli | 2009-02-10 |
| 7483327 | Apparatus and method for adjusting an operating parameter of an integrated circuit | Qadeer A. Qureshi, Jack M. Higman, Thomas Jew | 2009-01-27 |
| 7452768 | Multiple device types including an inverted-T channel transistor and method therefor | Byoung W. Min, Leo Mathew | 2008-11-18 |
| 7440313 | Two-port SRAM having improved write operation | Glenn C. Abeln, Lawrence N. Herr, Jack M. Higman | 2008-10-21 |
| 7414877 | Electronic device including a static-random-access memory cell and a process of forming the electronic device | Bich-Yen Nguyen, Brian A. Winstead | 2008-08-19 |
| 7403410 | Switch device and method | — | 2008-07-22 |
| 7352631 | Methods for programming a floating body nonvolatile memory | Ramachandran Muralidhar | 2008-04-01 |
| 7336533 | Electronic device and method for operating a memory circuit | Bradford Lawrence Hunter, Jack M. Higman | 2008-02-26 |
| 7292495 | Integrated circuit having a memory with low voltage read/write operation | Prashant U. Kenkare, Andrew C. Russell, David R. Bearden, Troy L. Cooper, Shayan Zhang | 2007-11-06 |
| 7285832 | Multiport single transistor bit cell | Alexander B. Hoefler | 2007-10-23 |
| 7269090 | Memory access with consecutive addresses corresponding to different rows | Frank K. Baker, Jr., Thomas Jew | 2007-09-11 |
| 7238555 | Single transistor memory cell with reduced programming voltages | Marius Orlowski | 2007-07-03 |
| 7238990 | Interlayer dielectric under stress for an integrated circuit | Jon D. Cheek | 2007-07-03 |
| 7195983 | Programming, erasing, and reading structure for an NVM cell | Gowrishankar L. Chindalore, Craig T. Swift, Ramachandran Muralidhar | 2007-03-27 |
| 7135379 | Isolation trench perimeter implant for threshold voltage control | Marius Orlowski | 2006-11-14 |
| 7105395 | Programming and erasing structure for an NVM cell | Gowrishankar L. Chindalore, Craig T. Swift, Ramachandran Muralidhar | 2006-09-12 |
| 7105430 | Method for forming a semiconductor device having a notched control electrode and structure thereof | Marius Orlowski | 2006-09-12 |