| 9595350 |
Hardware-based memory initialization |
Henning F. Spruth, Reinaldo Silveira |
2017-03-14 |
$17,718,000 |
| 9418741 |
Content addressable memory with search line test circuitry |
Ravindraraj Ramaraju, Henning F. Spruth, Reinaldo Silveira |
2016-08-16 |
|
| 9384856 |
Memories having a built-in self-test (BIST) feature |
Henning F. Spruth, Reinaldo Silveira |
2016-07-05 |
|
| 7616509 |
Dynamic voltage adjustment for memory |
Sushama Davar, Thomas Jew |
2009-11-10 |
|
| 7483327 |
Apparatus and method for adjusting an operating parameter of an integrated circuit |
James D. Burnett, Jack M. Higman, Thomas Jew |
2009-01-27 |
|
| 7444557 |
Memory with fault tolerant reference circuitry |
Alexander B. Hoefler |
2008-10-28 |
|
| 7362645 |
Integrated circuit fuses having corresponding storage circuitry |
John J. Vaglica, William C. Moyer, Ryan D. Bedwell |
2008-04-22 |
|
| 7295484 |
Temperature based DRAM refresh |
Arnaldo R. Cruz |
2007-11-13 |
|
| 7245527 |
Nonvolatile memory system using magneto-resistive random access memory (MRAM) |
Thomas Jew, Curtis F. Wyman |
2007-07-17 |
|
| 7206244 |
Temperature based DRAM refresh |
Arnaldo R. Cruz |
2007-04-17 |
|
| 6917555 |
Integrated circuit power management for reducing leakage current in circuit arrays and method therefor |
Ryan D. Bedwell, Christopher K. Y. Chun, John J. Vaglica |
2005-07-12 |
|
| 6791157 |
Integrated circuit package incorporating programmable elements |
James J. Casto, Hugh William Boothby |
2004-09-14 |
$2,721,000 |
| 6772356 |
System for specifying core voltage for a microprocessor by selectively outputting one of a first, fixed and a second, variable voltage control settings from the microprocessor |
Charles W. Mitchell, James J. Casto |
2004-08-03 |
$1,898,000 |
| 6711673 |
Using a model specific register as a base I/O address register for embedded I/O registers in a processor |
Charles W. Mitchell, Dervinn Caldwell |
2004-03-23 |
$3,151,000 |
| 6654860 |
Method and apparatus for removing speculative memory accesses from a memory access queue for issuance to memory or discarding |
Geoffrey S. Strongin |
2003-11-25 |
$4,814,000 |
| 6560688 |
System and method for improving accelerated graphics port systems |
Geoffrey S. Strongin |
2003-05-06 |
$2,132,000 |
| 6559850 |
Method and system for improved memory access in accelerated graphics port systems |
Geoffrey S. Strongin |
2003-05-06 |
$2,132,000 |
| 6546439 |
Method and system for improved data access |
Geoffrey S. Strongin |
2003-04-08 |
$2,382,000 |
| 6510497 |
Method and system for page-state sensitive memory control and access in data processing systems |
Geoffrey S. Strongin |
2003-01-21 |
$2,484,000 |
| 6421754 |
System management mode circuits, systems and methods |
Weiyuen Kau, John H. Cornish, Shannon A. Wichman |
2002-07-16 |
$34,449,000 |
| 6389556 |
Mechanism to prevent data loss in case of a power failure while a PC is in suspend to RAM state |
— |
2002-05-14 |
$2,737,000 |
| 6381672 |
Speculative opening of a new page when approaching page boundary during read/write of isochronous streams |
Geoffrey S. Strongin |
2002-04-30 |
$1,930,000 |
| 6381683 |
Method and system for destination-sensitive memory control and access in data processing systems |
Geoffrey S. Strongin |
2002-04-30 |
$1,930,000 |
| 6378076 |
Substantially undetectable data processing |
— |
2002-04-23 |
$2,653,000 |
| 6308237 |
Method and system for improved data transmission in accelerated graphics port systems |
Geoffrey S. Strongin |
2001-10-23 |
$2,669,000 |
