Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6976204 | Circuit and method for correcting erroneous data in memory for pipelined reads | Eric G. Chambers, James R. Magro | 2005-12-13 |
| 6775749 | System and method for performing a speculative cache fill | Mark T. Fox | 2004-08-10 |
| 6357024 | Electronic system and method for implementing functional redundancy checking by comparing signatures having relatively small numbers of signals | Drew J. Dutton, Scott White | 2002-03-12 |
| 6173395 | Mechanism to determine actual code execution flow in a computer | Michael T. Wisor, Travis Wheatley | 2001-01-09 |
| 5905898 | Apparatus and method for storing interrupt source information in an interrupt controller based upon interrupt priority | Qadeer A. Qureshi, James R. MacDonald, Douglas D. Gephardt, Rodney Schmidt | 1999-05-18 |
| 5894577 | Interrupt controller with external in-service indication for power management within a computer system | James R. MacDonald, Douglas D. Gephardt | 1999-04-13 |
| 5894578 | System and method for using random access memory in a programmable interrupt controller | Qadeer A. Qureshi, Joseph A. Bailey | 1999-04-13 |
| 5892956 | Serial bus for transmitting interrupt information in a multiprocessing system | Qadeer A. Qureshi, Joseph A. Bailey | 1999-04-06 |
| 5850555 | System and method for validating interrupts before presentation to a CPU | Qadeer A. Qureshi, Joseph A. Bailey | 1998-12-15 |
| 5850558 | System and method for referencing interrupt request information in a programmable interrupt controller | Qadeer A. Qureshi, Joseph A. Bailey | 1998-12-15 |
| 5778431 | System and apparatus for partially flushing cache memory | Saba Rahman, Victor F. Andrade | 1998-07-07 |
| 5765003 | Interrupt controller optimized for power management in a computer system or subsystem | James R. MacDonald, Douglas D. Gephardt | 1998-06-09 |
| 5682310 | Computer system including in-circuit emulation mode for debugging system management software | Michael D. Pedneau, Hans Magnusson | 1997-10-28 |
| 5655142 | High performance derived local bus and computer system employing the same | Douglas D. Gephardt | 1997-08-05 |
| 5561821 | System for performing I/O access and memory access by driving address of DMA configuration registers and memory address stored therein respectively on local bus | Douglas D. Gephardt, James R. MacDonald | 1996-10-01 |
| 5561819 | Computer system selecting byte lane for a peripheral device during I/O addressing technique of disabling non-participating peripherals by driving an address within a range on the local bus in a DMA controller | Douglas D. Gephardt, James R. MacDonald | 1996-10-01 |
| 5557757 | High performance integrated processor architecture including a sub-bus control unit for generating signals to control a secondary, non-multiplexed external bus | Douglas D. Gephardt, James R. MacDonald | 1996-09-17 |
| 5099140 | Synchronous clock source selector | — | 1992-03-24 |