Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date | Approx Value ⓘ |
|---|---|---|---|---|
| 5873114 | Integrated processor and memory control unit including refresh queue logic for refreshing DRAM during idle cycles | Victor F. Andrade | 1999-02-16 | $3,148,000 |
| 5778431 | System and apparatus for partially flushing cache memory | Dan S. Mudgett, Victor F. Andrade | 1998-07-07 | $3,620,000 |