Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5873114 | Integrated processor and memory control unit including refresh queue logic for refreshing DRAM during idle cycles | Victor F. Andrade | 1999-02-16 |
| 5778431 | System and apparatus for partially flushing cache memory | Dan S. Mudgett, Victor F. Andrade | 1998-07-07 |