Issued Patents All Time
Showing 26–50 of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8736071 | Semiconductor device with vias on a bridge connecting two buses | Douglas M. Reber, Mehul D. Shroff | 2014-05-27 |
| 8722519 | Integrated assist features for epitaxial growth | Omar Zia, Ruiqi Tian | 2014-05-13 |
| 8707231 | Method and system for derived layer checking for semiconductor device design | Douglas M. Reber, Mehul D. Shroff | 2014-04-22 |
| 8694926 | Techniques for checking computer-aided design layers of a device to reduce the occurrence of missing deck rules | Douglas M. Reber, Mehul D. Shroff | 2014-04-08 |
| 8640072 | Method for forming an electrical connection between metal layers | Douglas M. Reber, Mehul D. Shroff | 2014-01-28 |
| 8601430 | Device matching tool and methods thereof | Mehul D. Shroff, Douglas M. Reber | 2013-12-03 |
| 8595667 | Via placement and electronic circuit design processing method and electronic circuit design utilizing same | Mehul D. Shroff, Douglas M. Reber | 2013-11-26 |
| 8581390 | Semiconductor device with heat dissipation | Douglas M. Reber, Mehul D. Shroff | 2013-11-12 |
| 8003539 | Integrated assist features for epitaxial growth | Omar Zia, Ruiqi Tian | 2011-08-23 |
| 7858487 | Method and apparatus for indicating directionality in integrated circuit manufacturing | Mehul D. Shroff, Donald E. Smeltzer, Traci L. Smith | 2010-12-28 |
| 7635920 | Method and apparatus for indicating directionality in integrated circuit manufacturing | Mehul D. Shroff, Donald E. Smeltzer, Traci L. Smith | 2009-12-22 |
| 7622339 | EPI T-gate structure for CoSi2 extendibility | Mark D. Hall, Dharmesh Jawarani, Mehul D. Shroff | 2009-11-24 |
| 7565639 | Integrated assist features for epitaxial growth bulk tiles with compensation | Omar Zia, Nigel G. Cave, Venkat R. Kolagunta, Ruiqi Tian | 2009-07-21 |
| 7510922 | Spacer T-gate structure for CoSi2 extendibility | Mark D. Hall, Dharmesh Jawarani, Mehul D. Shroff | 2009-03-31 |
| 7470624 | Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation | Omar Zia, Nigel G. Cave, Venkat R. Kolagunta, Ruiqi Tian | 2008-12-30 |
| 7386821 | Primitive cell method for front end physical design | Jack M. Higman, Ertugrul Demircan | 2008-06-10 |
| 7322014 | Method of implementing polishing uniformity and modifying layout data | Nathan A. Aldrich, Ruiqi Tian | 2008-01-22 |
| 7276435 | Die level metal density gradient for improved flip chip package reliability | Scott K. Pozder, Kevin J. Hess, Ruiqi Tian, Trent S. Uehling, Brett P. Wilkerson +1 more | 2007-10-02 |
| 7247552 | Integrated circuit having structural support for a flip-chip interconnect pad and method therefor | Scott K. Pozder, Kevin J. Hess, Pak K. Leung, Brett P. Wilkerson, David G. Wontor +1 more | 2007-07-24 |
| 7238579 | Semiconductor device for reducing photovolatic current | Bradley P. Smith | 2007-07-03 |
| 7146593 | Method of implementing polishing uniformity and modifying layout data | Nathan A. Aldrich, Ruiqi Tian | 2006-12-05 |
| 6956281 | Semiconductor device for reducing photovolatic current | Bradley P. Smith | 2005-10-18 |
| 6905967 | Method for improving planarity of shallow trench isolation using multiple simultaneous tiling systems | Ruiqi Tian, Thomas M. Brown | 2005-06-14 |
| 6764919 | Method for providing a dummy feature and structure thereof | Kathleen C. Yu, Bradley P. Smith | 2004-07-20 |
| 6613688 | Semiconductor device and process for generating an etch pattern | Thomas M. Brown, Jeffrey C. Haines | 2003-09-02 |