Issued Patents All Time
Showing 51–67 of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7219176 | System and apparatus for early fixed latency subtractive decoding | Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu, Hang T. Nguyen | 2007-05-15 |
| 7194671 | Mechanism handling race conditions in FRC-enabled processors | Steven Tu, Alexander J. Honcharik, Hang T. Nguyen, Quinn W. Merrell | 2007-03-20 |
| 7159077 | Direct processor cache access within a system having a coherent multi-processor protocol | Steven Tu, Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Hang T. Nguyen | 2007-01-02 |
| 7143220 | Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latencies | Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu, Hang T. Nguyen | 2006-11-28 |
| 7120755 | Transfer of cache lines on-chip between processing cores in a multi-core system | Quinn W. Merrell, Cameron McNairy | 2006-10-10 |
| 7100001 | Methods and apparatus for cache intervention | Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu, Mark Fullerton +1 more | 2006-08-29 |
| 7062613 | Methods and apparatus for cache intervention | Hang T. Nguyen, Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu | 2006-06-13 |
| 7055060 | On-die mechanism for high-reliability processor | Hang T. Nguyen, Steven Tu, Alexander J. Honcharik | 2006-05-30 |
| 7003632 | Method and apparatus for scalable disambiguated coherence in shared storage hierarchies | Hang T. Nguyen, Quinn W. Merrell | 2006-02-21 |
| 6983348 | Methods and apparatus for cache intervention | Hang T. Nguyen, Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu | 2006-01-03 |
| 6775748 | Methods and apparatus for transferring cache block ownership | Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu | 2004-08-10 |
| 6718494 | Method and apparatus for preventing and recovering from TLB corruption by soft error | Hang Hguyen | 2004-04-06 |
| 6658621 | System and method for silent data corruption prevention due to next instruction pointer corruption by soft errors | Hang T. Nguyen, Andres Rabago | 2003-12-02 |
| 6651145 | Method and apparatus for scalable disambiguated coherence in shared storage hierarchies | Hang T. Nguyen, Quinn W. Merrell | 2003-11-18 |
| 6543028 | Silent data corruption prevention due to instruction corruption by soft errors | Hang T. Nguyen, Andres Rabago | 2003-04-01 |
| 6304960 | Validating prediction for branches in a cluster via comparison of predicted and condition selected tentative target addresses and validation of branch conditions | Tse-Yu Yeh, Michael Corwin, Judge K. Arora, Sailesh Kottapalli | 2001-10-16 |
| 6240510 | System for processing a cluster of instructions where the instructions are issued to the execution units having a priority order according to a template associated with the cluster of instructions | Tse-Yu Yeh, Harshvardhan Sharangpani, Michael Corwin | 2001-05-29 |