Issued Patents All Time
Showing 26–50 of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8135916 | Method and apparatus for hardware-configurable multi-policy coherence protocol | R. Frank O'Bleness, David E. Miner, Joseph Delgross, Tom Hameenanttila, Jeffrey Kehl | 2012-03-13 |
| 8099448 | Arithmetic logic and shifting device for use in a processor | Muhammad Ahmed, Ajay Anant Ingle | 2012-01-17 |
| 7966477 | Power optimized replay of blocked operations in a pipilined architecture | Hang T. Nguyen, Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu | 2011-06-21 |
| 7917907 | Method and system for variable thread allocation and switching in a multithreaded processor | Muhammad Ahmed, Erich James Plondke, Lucian Codrescu, William C. Anderson | 2011-03-29 |
| 7849466 | Controlling execution mode of program threads by applying a mask to a control register in a multi-threaded processor | Lucian Codrescu, Donald Robert Padgett, Erich James Plondke, Taylor Simpson, Muhammad Ahmed +1 more | 2010-12-07 |
| 7765349 | Apparatus and method for arbitrating heterogeneous agents in on-chip busses | Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu, Hang T. Nguyen | 2010-07-27 |
| 7757046 | Method and apparatus for optimizing line writes in cache coherent systems | Hang T. Nguyen, Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu | 2010-07-13 |
| 7725683 | Apparatus and method for power optimized replay via selective recirculation of instructions | Hang T. Nguyen, Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu | 2010-05-25 |
| 7694080 | Method and apparatus for providing a low power mode for a processor while maintaining snoop throughput | Quinn W. Merrell, R. Frank O'Bleness, Hang T. Nguyen | 2010-04-06 |
| 7685379 | Cache memory to support a processor's power mode of operation | Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu | 2010-03-23 |
| 7640387 | Method and apparatus for implementing heterogeneous interconnects | Samantha J. Edirisooriya, Steven Tu, Gregory Tse, David E. Miner, R. Frank O'Bleness +1 more | 2009-12-29 |
| 7634603 | System and apparatus for early fixed latency subtractive decoding | Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu, Hang T. Nguyen | 2009-12-15 |
| 7620778 | Low power microprocessor cache memory and method of operation | Baker Mohammad, Muhammad Ahmed, Paul Bassett, Ajay Anant Ingle | 2009-11-17 |
| 7523295 | Processor and method of grouping and executing dependent instructions in a packet | Lucian Codrescu, Erich James Plondke, Muhammad Ahmed, William C. Anderson | 2009-04-21 |
| 7487299 | Cache memory to support a processor's power mode of operation | Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu | 2009-02-03 |
| 7464227 | Method and apparatus for supporting opportunistic sharing in coherent multiprocessors | Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu, Hang T. Nguyen | 2008-12-09 |
| 7428607 | Apparatus and method for arbitrating heterogeneous agents in on-chip busses | Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu, Hang T. Nguyen | 2008-09-23 |
| 7415633 | Method and apparatus for preventing and recovering from TLB corruption by soft error | Hang T. Nguyen | 2008-08-19 |
| 7406552 | Systems and methods for early fixed latency subtractive decoding including speculative acknowledging | Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu, Hang T. Nguyen | 2008-07-29 |
| 7406553 | System and apparatus for early fixed latency subtractive decoding | Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu, Hang T. Nguyen | 2008-07-29 |
| 7404043 | Cache memory to support a processor's power mode of operation | Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu | 2008-07-22 |
| 7366845 | Pushing of clean data to one or more processors in a system having a coherency protocol | Hang T. Nguyen, Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu | 2008-04-29 |
| 7353317 | Method and apparatus for implementing heterogeneous interconnects | Samantha J. Edirisooriya, Steven Tu, Gregory Tse, David E. Miner, R. Frank O'Bleness +1 more | 2008-04-01 |
| 7290093 | Cache memory to support a processor's power mode of operation | Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu | 2007-10-30 |
| 7234028 | Power/performance optimized cache using memory write prevention through write snarfing | Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu | 2007-06-19 |