AS

Alex See

CM Chartered Semiconductor Manufacturing: 39 patents #11 of 840Top 2%
GP Globalfoundries Singapore Pte.: 15 patents #42 of 828Top 6%
NS National University Of Singapore: 3 patents #115 of 1,623Top 8%
IE Institute Of Materials Research And Engineering: 1 patents #14 of 38Top 40%
📍 Singapore, SG: #57 of 13,971 inventorsTop 1%
Overall (All Time): #46,213 of 4,157,543Top 2%
55
Patents All Time

Issued Patents All Time

Showing 26–50 of 55 patents

Patent #TitleCo-InventorsDate
6764914 Method of forming a high K metallic dielectric layer Cher Liang Cha, Shyue Fong Quek, Ting Cheong Ang, Wye Boon Loh, Sang Yee Loong +2 more 2004-07-20
6734072 Method of fabricating a MOSFET device using a spike rapid thermal oxidation procedure Yung Fu Chong 2004-05-11
6727151 Method to fabricate elevated source/drain structures in MOS transistors Yung Fu Chong, Randall Cher Liang Cha 2004-04-27
6680239 Effective isolation with high aspect ratio shallow trench isolation and oxygen or field implant Cher Liang Cha, Kok Keng Ong, Lap Chan 2004-01-20
6650220 Parallel spiral stacked inductor on semiconductor material Choon-Beng Sia, Kiat Seng Yeo, Toe Naing Swe, Cheng Yeow Ng 2003-11-18
6638365 Method for obtaining clean silicon surfaces for semiconductor manufacturing Jianhui Ye, Simon Chooi 2003-10-28
6630405 Method of gate patterning for sub-0.1 &mgr;m technology Lai Weng Hong 2003-10-07
6624489 Formation of silicided shallow junctions using implant through metal technology and laser annealing process Yung Fu Chong, Kin Leong Pey 2003-09-23
6613652 Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance Yeow Kheng Lim, Randall Cher Liang Cha, Tae Jong Lee, Wang Ling Goh 2003-09-02
6602801 Method for forming a region of low dielectric constant nanoporous material Siew Yong Kong, Simon Chooi, Gautam Sarkar 2003-08-05
6492242 Method of forming of high K metallic dielectric layer Cher Liang Cha, Shyuz Fong Quek, Ting Cheong Ang, Wye Boon Loh, Sang Yee Loong +2 more 2002-12-10
6475875 Shallow trench isolation elevation uniformity via insertion of a polysilicon etch layer Pang Chong Hau, Chen Feng, Peter Hing 2002-11-05
6472697 Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application Yeow Kheng Lim, Randall Cher Liang Cha, Wang Ling Goh, Victor Lim 2002-10-29
6468880 Method for fabricating complementary silicon on insulator devices using wafer bonding Yeow Kheng Lim, Randall Cher Liang Cha, Tae Jong Lee, Wang Ling Goh 2002-10-22
6436833 Method for pre-STI-CMP planarization using poly-si thermal oxidation Chong Hau Pang, Chen Feng, Peter Hing 2002-08-20
6432797 Simplified method to reduce or eliminate STI oxide divots Randall Cher Liang Cha, Tae Jong Lee, Lap Chan, Yeow Kheng Lim 2002-08-13
6399471 Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application Yeow Kheng Lim, Randall Cher Liang Cha, Wang Ling Goh, Victor Lim 2002-06-04
6391720 Process flow for a performance enhanced MOSFET with self-aligned, recessed channel Sneedharan Pillai Sneelal, Francis Poh, James Yong Meng Lee, C. K. Lau, Ganesh Samudra 2002-05-21
6391731 Activating source and drain junctions and extensions using a single laser anneal Yung Fu Chong, Kin Leong Pey 2002-05-21
6387747 Method to fabricate RF inductors with minimum area Randall Cher Liang Cha, Tae Jong Lee, Lap Chan, Chua Chee Tee 2002-05-14
6380066 Methods for eliminating metal corrosion by FSG Kok Hin Teo, Kok Hiang Tang 2002-04-30
6365446 Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing process Yung Fu Chong, Kin Leong Pey 2002-04-02
6355563 Versatile copper-wiring layout design with low-k dielectric integration Randall Cher Liang Cha, Yeow Kheng Lim, Tae Jong Lee, Lap Chan 2002-03-12
6348385 Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constant Randall Cher Liang Cha, Tae Jong Lee, Lap Chan, Chee Tee Chua 2002-02-19
6335253 Method to form MOS transistors with shallow junctions using laser annealing Yung Fu Chong, Kin Leong Pey, Andrew Thye Shen Wee 2002-01-01