Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12033964 | Chemical mechanical polishing for copper dishing control | Tyler Sherwood, Joseph F. Salfelder, Ki Cheol Ahn, Raghav Sreenivasan, Jason Appell | 2024-07-09 |
| 10879177 | PVD deposition and anneal of multi-layer metal-dielectric film | Minrui Yu, Thomas Jongwan Kwon, Kaushal K. Singh, Er-Xuan Ping | 2020-12-29 |
| 9496253 | Miniature passive structures, high frequency electrostatic discharge protection networks, and high frequency electrostatic discharge protection schemes | Keping Wang, Kiat Seng Yeo | 2016-11-15 |
| 9431237 | Post treatment methods for oxide layers on semiconductor devices | Christopher S. Olsen, Yoshitaka Yokota | 2016-08-30 |
| 9373876 | Multiple-mode filter for radio frequency integrated circuits | Kok Meng Lim, Kiat Seng Yeo, Jian Guo Ma | 2016-06-21 |
| 9337157 | Miniature passive structures for ESD protection and input and output matching | Yang Lu, Jiangmin Gu, Kiat Seng Yeo | 2016-05-10 |
| 9331659 | Integrated circuit architecture with strongly coupled LC tanks | Nagarajan Mahalingam, Shouxian Mou, Kiat Seng Yeo | 2016-05-03 |
| 9288225 | Server port sharing based on shared socket | Gong Fei, Zhenghua Xu, Alexey Shvechkov | 2016-03-15 |
| 9154104 | Miniaturized passive low pass filter | Shouxian Mou, Kiat Seng Yeo | 2015-10-06 |
| 9130511 | Power amplifier and linearization techniques using active and passive devices | Jiangmin Gu, Yang Lu, Kiat Seng Yeo | 2015-09-08 |
| 8319149 | Radiant anneal throughput optimization and thermal history minimization by interlacing | Abhilash J. Mayur, Vijay Parihar | 2012-11-27 |
| 8309475 | Apparatus and method of aligning and positioning a cold substrate on a hot surface | Blake Koelmel, Abhilash J. Mayur, Alexander Lerner | 2012-11-13 |
| 8097543 | Apparatus and method of aligning and positioning a cold substrate on a hot surface | Blake Koelmel, Abhilash J. Mayur, Alexander Lerner | 2012-01-17 |
| 8043981 | Dual frequency low temperature oxidation of a semiconductor device | Yoshitaka Yokota, Christopher S. Olsen | 2011-10-25 |
| 7429532 | Semiconductor substrate process using an optically writable carbon-containing mask | Kartik Ramaswamy, Hiroji Hanawa, Biagio Gallo, Kenneth S. Collins, Vijay Parihar +4 more | 2008-09-30 |
| 7422775 | Process for low temperature plasma deposition of an optical absorption layer and high speed optical annealing | Kartik Ramaswamy, Hiroji Hanawa, Biagio Gallo, Kenneth S. Collins, Vijay Parihar +4 more | 2008-09-09 |
| 7335611 | Copper conductor annealing process employing high speed optical annealing with a low temperature-deposited optical absorber layer | Kartik Ramaswamy, Hiroji Hanawa, Biagio Gallo, Kenneth S. Collins, Vijay Parihar +4 more | 2008-02-26 |
| 7323401 | Semiconductor substrate process using a low temperature deposited carbon-containing hard mask | Kartik Ramaswamy, Hiroji Hanawa, Biagio Gallo, Kenneth S. Collins, Vijay Parihar +4 more | 2008-01-29 |
| 7312148 | Copper barrier reflow process employing high speed optical annealing | Kartik Ramaswamy, Hiroji Hanawa, Biagio Gallo, Kenneth S. Collins, Vijay Parihar +4 more | 2007-12-25 |
| 7312162 | Low temperature plasma deposition process for carbon layer deposition | Kartik Ramaswamy, Hiroji Hanawa, Biagio Gallo, Kenneth S. Collins, Vijay Parihar +4 more | 2007-12-25 |
| 7109098 | Semiconductor junction formation process including low temperature plasma deposition of an optical absorption layer and high speed optical annealing | Kartik Ramaswamy, Hiroji Hanawa, Biagio Gallo, Kenneth S. Collins, Vijay Parihar +4 more | 2006-09-19 |