Issued Patents All Time
Showing 26–38 of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11145504 | Method of forming film stacks with reduced defects | Zhijun Jiang, Ganesh Balasubramanian, Arkajit Roy Barman, Hidehiro Kojiri, Xinhai Han +8 more | 2021-10-12 |
| 10990818 | Virtual reality device with iris acquisition function | Rongguan Zhou | 2021-04-27 |
| 10706280 | Virtual reality device with iris acquisition function | Rongguan Zhou | 2020-07-07 |
| 7129134 | Fabrication method for flash memory source line and flash memory | Jui-Hsiang Yang, Ing-Ruey Liaw | 2006-10-31 |
| 6734504 | Method of providing HBM protection with a decoupled HBM structure | James H. Lie | 2004-05-11 |
| 6525962 | High current and/or high speed electrically erasable memory cell for programmable logic devices | Sheng Yueh Pai, Kevin Yen | 2003-02-25 |
| 6294474 | Process for controlling oxide thickness over a fusible link using transient etch stops | Wen-Tsing Tzeng, Kau-Jan Wang | 2001-09-25 |
| 6150213 | Method of forming a cob dram by using self-aligned node and bit line contact plug | Hung-Yi Luo, Erik S. Jeng | 2000-11-21 |
| 6143664 | Method of planarizing a structure having an interpoly layer | Liang-Gi Yao, Chung-Ju Lee, Wei-Ray Lin, Yeur-Luen Tu | 2000-11-07 |
| 6100137 | Etch stop layer used for the fabrication of an overlying crown shaped storage node structure | Liang-Gi Yao, Guei-Chi Guo, Hung-Yi Luo | 2000-08-08 |
| 6037211 | Method of fabricating contact holes in high density integrated circuits using polysilicon landing plug and self-aligned etching processes | Erik S. Jeng, Bi-Ling Chen | 2000-03-14 |
| 6033962 | Method of fabricating sidewall spacers for a self-aligned contact hole | Erik S. Jeng, Hung-Yi Luo, Ming-Horn Tsai | 2000-03-07 |
| 5904521 | Method of forming a dynamic random access memory | Erik S. Jeng | 1999-05-18 |