Issued Patents All Time
Showing 76–100 of 161 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9040349 | Method and system for a semiconductor device package with a die to interposer wafer first bond | Michael Kelly, Won Chul Do, David Jon Hiner | 2015-05-26 |
| 8987050 | Method and system for backside dielectric patterning for wafer warpage and stress control | David Jon Hiner, Michael Kelly | 2015-03-24 |
| 8952522 | Wafer level package and fabrication method | Sukianto Rusli, David Razu | 2015-02-10 |
| 8941250 | Electronic component package fabrication method and structure | Robert Francis Darveaux, Brett Dunlap | 2015-01-27 |
| 8872329 | Extended landing pad substrate package structure and method | David Jon Hiner | 2014-10-28 |
| 8826531 | Method for making an integrated circuit substrate having laminated laser-embedded circuit layers | David Jon Hiner, Sukianto Rusli | 2014-09-09 |
| 8802499 | Methods for temporary wafer molding for chip-on-wafer assembly | Michael Kelly, David Jon Hiner | 2014-08-12 |
| 8796072 | Method and system for a semiconductor device package with a die-to-die first bond | Michael Kelly, Won Chul Do | 2014-08-05 |
| 8710649 | Wafer level package and fabrication method | Sukianto Rusli, David Razu | 2014-04-29 |
| 8704369 | Flip chip bump structure and fabrication method | Roger D. St. Amand, Robert Francis Darveaux | 2014-04-22 |
| 8691632 | Wafer level package and fabrication method | Sukianto Rusli, David Razu | 2014-04-08 |
| 8653674 | Electronic component package fabrication method and structure | Robert Francis Darveaux, Brett Dunlap | 2014-02-18 |
| 8551820 | Routable single layer substrate and semiconductor package including same | Donald C. Foster | 2013-10-08 |
| 8501543 | Direct-write wafer level chip scale package | Christopher J. Berry, David Jon Hiner | 2013-08-06 |
| 8486764 | Wafer level package and fabrication method | Sukianto Rusli, David Razu | 2013-07-16 |
| 8440554 | Through via connected backside embedded circuit features structure and method | David Jon Hiner | 2013-05-14 |
| 8432022 | Shielded embedded electronic component substrate fabrication method and structure | Brett Dunlap, David Jon Hiner | 2013-04-30 |
| 8426966 | Bumped chip package | Rex Anderson, Ravi Kiran Chilukuri | 2013-04-23 |
| 8390130 | Through via recessed reveal structure and method | David Jon Hiner, Michael Kelly | 2013-03-05 |
| 8390116 | Flip chip bump structure and fabrication method | Roger D. St. Amand, Robert Francis Darveaux | 2013-03-05 |
| 8383950 | Metal etch stop fabrication method and structure | Sukianto Rusli, Robert Francis Darveaux | 2013-02-26 |
| 8341835 | Buildup dielectric layer having metallization pattern semiconductor package fabrication method | Sukianto Rusli, David Jon Hiner | 2013-01-01 |
| 8322030 | Circuit-on-foil process for manufacturing a laminated semiconductor package substrate having embedded conductive patterns | Sukianto Rusli | 2012-12-04 |
| 8323771 | Straight conductor blind via capture pad structure and fabrication method | Sukianto Rusli | 2012-12-04 |
| 8324511 | Through via nub reveal method and structure | Frederick Evans Reed, David Jon Hiner, Kiwook Lee | 2012-12-04 |