Issued Patents All Time
Showing 51–73 of 73 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7089527 | Structures and methods for selectively applying a well bias to portions of a programmable device | Steven P. Young, Stephen M. Trimberger | 2006-08-08 |
| 6982451 | Single event upset in SRAM cells in FPGAs with high resistivity gate structures | Martin L. Voogel, Austin H. Lesea, Joseph J. Fabula, Carl H. Carmichael, Shahin Toutounchi +3 more | 2006-01-03 |
| 6949951 | Integrated circuit multiplexer including transistors of more than one oxide thickness | Steven P. Young, Venu M. Kondapalli, Martin L. Voogel | 2005-09-27 |
| 6777978 | Structures and methods for selectively applying a well bias to portions of a programmable device | Steven P. Young, Stephen M. Trimberger | 2004-08-17 |
| 6768335 | Integrated circuit multiplexer including transistors of more than one oxide thickness | Steven P. Young, Venu M. Kondapalli, Martin L. Voogel | 2004-07-27 |
| 6645802 | Method of forming a zener diode | Sheau-Suey Li, Shahin Toutounchi, Xin Wu, Daniel Gitlin | 2003-11-11 |
| 6621325 | Structures and methods for selectively applying a well bias to portions of a programmable device | Steven P. Young, Daniel Gitlin, Hua Shen, Stephen M. Trimberger | 2003-09-16 |
| 6549458 | Non-volatile memory array using gate breakdown structures | Kameswara K. Rao, Martin L. Voogel, James Karp, Shahin Toutounchi, Daniel Gitlin +3 more | 2003-04-15 |
| 6522582 | Non-volatile memory array using gate breakdown structures | Kameswara K. Rao, Martin L. Voogel, James Karp, Shahin Toutounchi, Daniel Gitlin +3 more | 2003-02-18 |
| 6438065 | Redundancy architecture and method for non-volatile storage | Kameswara K. Rao, Martin L. Voogel | 2002-08-20 |
| 6432808 | Method of improved bondability when using fluorinated silicon glass | James Karp | 2002-08-13 |
| 6268639 | Electrostatic-discharge protection circuit | Sheau-Suey Li, Shahin Toutounchi, Xin Wu, Daniel Gitlin | 2001-07-31 |
| 6243294 | Memory architecture for non-volatile storage using gate breakdown structure in standard sub 0.35 micron process | Kameswara K. Rao, Martin L. Voogel | 2001-06-05 |
| 6057589 | Method for over-etching to improve voltage distribution | Kevin T. Look, Yakov Karpovich | 2000-05-02 |
| 6033938 | Antifuse with improved on-state reliability | Martin L. Voogel, Yakov Karpovich | 2000-03-07 |
| 5970372 | Method of forming multilayer amorphous silicon antifuse | Kevin T. Look, Yakov Karpovich | 1999-10-19 |
| 5870327 | Mixed mode RAM/ROM cell using antifuses | Daniel Gitlin, Dennis L. Segers | 1999-02-09 |
| 5786240 | Method for over-etching to improve voltage distribution | Kevin T. Look, Yakov Karpovich | 1998-07-28 |
| 5768179 | Antifuse load sram cell | — | 1998-06-16 |
| 5726484 | Multilayer amorphous silicon antifuse | Kevin T. Look, Yakov Karpovich | 1998-03-10 |
| 5455790 | High density EEPROM cell array which can selectively erase each byte of data in each row of the array | Albert Bergemont | 1995-10-03 |
| 5293331 | High density EEPROM cell with tunnel oxide stripe | Albert Bergemont | 1994-03-08 |
| 5108939 | Method of making a non-volatile memory cell utilizing polycrystalline silicon spacer tunnel region | Martin H. Manley, Philip John Cacharelis | 1992-04-28 |