Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9601613 | Gate pullback at ends of high-voltage vertical transistor structure | Vijay Parthasarathy | 2017-03-21 |
| 9112017 | Integrated transistor and anti-fuse as programming element for a high-voltage integrated circuit | Sujit Banerjee | 2015-08-18 |
| 8816433 | Checkerboarded high-voltage vertical transistor layout | Vijay Parthasarathy, Sujit Banerjee | 2014-08-26 |
| 8653583 | Sensing FET integrated with a high-voltage transistor | Vijay Parthasarathy, Sujit Banerjee | 2014-02-18 |
| 8513719 | Integrated transistor and anti-fuse programming element for a high-voltage integrated circuit | Sujit Banerjee | 2013-08-20 |
| 8410551 | Checkerboarded high-voltage vertical transistor layout | Vijay Parthasarathy, Sujit Banerjee | 2013-04-02 |
| 8222691 | Gate pullback at ends of high-voltage vertical transistor structure | Vijay Parthasarathy | 2012-07-17 |
| 8164125 | Integrated transistor and anti-fuse as programming element for a high-voltage integrated circuit | Sujit Banerjee | 2012-04-24 |
| 8022456 | Checkerboarded high-voltage vertical transistor layout | Vijay Parthasarathy, Sujit Banerjee | 2011-09-20 |
| 7859037 | Checkerboarded high-voltage vertical transistor layout | Vijay Parthasarathy, Sujit Banerjee | 2010-12-28 |
| 7595523 | Gate pullback at ends of high-voltage vertical transistor structure | Vijay Parthasarathy | 2009-09-29 |
| 6410413 | Semiconductor device with transparent link area for silicide applications and fabrication thereof | Gregory S. Scott, Emmanuel de Muizon | 2002-06-25 |
| 6326675 | Semiconductor device with transparent link area for silicide applications and fabrication thereof | Gregory S. Scott, Emmanuel de Muizon | 2001-12-04 |
| 6235557 | Programmable fuse and method therefor | — | 2001-05-22 |
| 6221735 | Method for eliminating stress induced dislocations in CMOS devices | Faran Nouri | 2001-04-24 |
| 5976943 | Method for bi-layer programmable resistor | Robert L. Payne | 1999-11-02 |
| 5962911 | Semiconductor devices having amorphous silicon antifuse structures | — | 1999-10-05 |
| 5882998 | Low power programmable fuse structures and methods for making the same | Harlan Lee Sur, Jr., Subhas Bothra, Xi-Wei Lin, Robert L. Payne | 1999-03-16 |
| 5854510 | Low power programmable fuse structures | Harlan Lee Sur, Jr., Subhas Bothra, Xi-Wei Lin, Robert L. Payne | 1998-12-29 |
| 5723358 | Method of manufacturing amorphous silicon antifuse structures | — | 1998-03-03 |
| 5517453 | Memory with multiple erase modes | Robert J. Strain | 1996-05-14 |
| 5404037 | EEPROM cell with the drain diffusion region self-aligned to the tunnel oxide region | — | 1995-04-04 |
| 5284784 | Buried bit-line source-side injection flash memory cell | — | 1994-02-08 |
| 5115288 | Split-gate EPROM cell using polysilicon spacers | — | 1992-05-19 |
| 5108939 | Method of making a non-volatile memory cell utilizing polycrystalline silicon spacer tunnel region | Michael J. Hart, Philip John Cacharelis | 1992-04-28 |