Issued Patents All Time
Showing 51–73 of 73 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6822894 | Single event upset in SRAM cells in FPGAs with leaky gate transistors | Philip D. Costello | 2004-11-23 |
| 6768335 | Integrated circuit multiplexer including transistors of more than one oxide thickness | Steven P. Young, Michael J. Hart, Venu M. Kondapalli | 2004-07-27 |
| 6768338 | PLD lookup table including transistors of more than one oxide thickness | Steven P. Young, Venu M. Kondapalli | 2004-07-27 |
| 6753722 | Method and apparatus for voltage regulation within an integrated circuit | Venu M. Kondapalli, Philip D. Costello | 2004-06-22 |
| 6621289 | Method and test circuit for developing integrated circuit fabrication processes | — | 2003-09-16 |
| 6549458 | Non-volatile memory array using gate breakdown structures | Kameswara K. Rao, James Karp, Shahin Toutounchi, Michael J. Hart, Daniel Gitlin +3 more | 2003-04-15 |
| 6522582 | Non-volatile memory array using gate breakdown structures | Kameswara K. Rao, James Karp, Shahin Toutounchi, Michael J. Hart, Daniel Gitlin +3 more | 2003-02-18 |
| 6509739 | Method for locating defects and measuring resistance in a test structure | Leon Ly Nguyen, Narasimhan Vasudevan | 2003-01-21 |
| 6438065 | Redundancy architecture and method for non-volatile storage | Kameswara K. Rao, Michael J. Hart | 2002-08-20 |
| 6362651 | Method for fabricating PLDs including multiple discrete devices formed on a single chip | — | 2002-03-26 |
| 6281696 | Method and test circuit for developing integrated circuit fabrication processes | — | 2001-08-28 |
| 6243294 | Memory architecture for non-volatile storage using gate breakdown structure in standard sub 0.35 micron process | Kameswara K. Rao, Michael J. Hart | 2001-06-05 |
| 6208549 | One-time programmable poly-fuse circuit for implementing non-volatile functions in a standard sub 0.35 micron CMOS | Kameswara K. Rao | 2001-03-27 |
| 6157213 | Layout architecture and method for fabricating PLDs including multiple discrete devices formed on a single chip | — | 2000-12-05 |
| 6137714 | Dynamic memory cell for a programmable logic device | — | 2000-10-24 |
| 6055205 | Decoder for a non-volatile memory array using gate breakdown structure in standard sub 0.35 micron CMOS process | Kameswara K. Rao | 2000-04-25 |
| 6044012 | Non-volatile memory array using gate breakdown structure in standard sub 0.35 micron CMOS process | Kameswara K. Rao, Shahin Toutounchi, James Karp | 2000-03-28 |
| 6033938 | Antifuse with improved on-state reliability | Yakov Karpovich, Michael J. Hart | 2000-03-07 |
| 5986958 | DRAM configuration in PLDs | — | 1999-11-16 |
| 5959821 | Triple-well silicon controlled rectifier with dynamic holding voltage | — | 1999-09-28 |
| 5949712 | Non-volatile memory array using gate breakdown structure | Kameswara K. Rao | 1999-09-07 |
| 5880620 | Pass gate circuit with body bias control | Daniel Gitlin, Sheau-Suey Li, Tiemin Zhao | 1999-03-09 |
| 5835402 | Non-volatile storage for standard CMOS integrated circuits | Kameswara K. Rao | 1998-11-10 |