Issued Patents All Time
Showing 26–50 of 73 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8344755 | Configuration context switcher | Trevis Chandler, Jason Redgrave | 2013-01-01 |
| 8324931 | Configuration context switcher with a latch | Jason Redgrave, Trevis Chandler | 2012-12-04 |
| 8248101 | Reading configuration data from internal storage node of configuration storage circuit | Jason Redgrave, Trevis Chandler | 2012-08-21 |
| 8138789 | Configuration context switcher with a clocked storage element | Trevis Chandler, Joe Entjer, Jason Redgrave | 2012-03-20 |
| 7928761 | Configuration context switcher with a latch | Jason Redgrave, Trevis Chandler | 2011-04-19 |
| 7907461 | Structures and methods of preventing an unintentional state change in a data storage node of a latch | Chi M. Nguyen | 2011-03-15 |
| 7859918 | Method and apparatus for trimming die-to-die variation of an on-chip generated voltage reference | Leon Ly Nguyen | 2010-12-28 |
| 7825685 | Configuration context switcher with a clocked storage element | Trevis Chandler, Joe Entjer, Jason Redgrave | 2010-11-02 |
| 7504877 | Charge pump and voltage regulator for body bias voltage | Ly Nguyen | 2009-03-17 |
| 7452765 | Single event upset in SRAM cells in FPGAs with high resistivity gate structures | Austin H. Lesea, Joseph J. Fabula, Carl H. Carmichael, Shahin Toutounchi, Michael J. Hart +3 more | 2008-11-18 |
| 7400123 | Voltage regulator with variable drive strength for improved phase margin in integrated circuits | — | 2008-07-15 |
| 7385416 | Circuits and methods of implementing flip-flops in dual-output lookup tables | Manoj Chirania | 2008-06-10 |
| 7378869 | Lookup table circuits programmable to implement flip-flops | Manoj Chirania | 2008-05-27 |
| 7376000 | Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets | Steven P. Young | 2008-05-20 |
| 7301796 | Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets | Steven P. Young | 2007-11-27 |
| 7283409 | Data monitoring for single event upset in a programmable logic device | David P. Schultz, Vasisht Mantra Vadi, Philip D. Costello, Venu M. Kondapalli | 2007-10-16 |
| 7239173 | Programmable memory element with power save mode in a programmable logic device | — | 2007-07-03 |
| 7119570 | Method of measuring performance of a semiconductor device and circuit for the same | Manoj Chirania, Venu M. Kondapalli, Philip D. Costello | 2006-10-10 |
| 7109783 | Method and apparatus for voltage regulation within an integrated circuit | Venu M. Kondapalli, Philip D. Costello | 2006-09-19 |
| 7109746 | Data monitoring for single event upset in a programmable logic device | David P. Schultz, Vasisht Mantra Vadi, Philip D. Costello, Venu M. Kondapalli | 2006-09-19 |
| 7110281 | Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets | Steven P. Young | 2006-09-19 |
| 7064574 | PLD memory cells utilizing metal-to-metal capacitors to selectively reduce susceptibility to single event upsets | Steven P. Young | 2006-06-20 |
| 7053654 | PLD lookup table including transistors of more than one oxide thickness | Steven P. Young, Venu M. Kondapalli | 2006-05-30 |
| 6982451 | Single event upset in SRAM cells in FPGAs with high resistivity gate structures | Austin H. Lesea, Joseph J. Fabula, Carl H. Carmichael, Shahin Toutounchi, Michael J. Hart +3 more | 2006-01-03 |
| 6949951 | Integrated circuit multiplexer including transistors of more than one oxide thickness | Steven P. Young, Michael J. Hart, Venu M. Kondapalli | 2005-09-27 |