Issued Patents All Time
Showing 26–50 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6949436 | Composite spacer liner for improved transistor performance | James F. Buller, Scott Luning, Derick J. Wristers, Daniel Kadosh | 2005-09-27 |
| 6921704 | Method for improving MOS mobility | Akif Sultan, Bin Yu | 2005-07-26 |
| 6872583 | Test structure for high precision analysis of a semiconductor | — | 2005-03-29 |
| 6864516 | SOI MOSFET junction degradation using multiple buried amorphous layers | Andy Wei, Akif Sultan | 2005-03-08 |
| 6784101 | Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation | Bin Yu | 2004-08-31 |
| 6777281 | Maintaining LDD series resistance of MOS transistors by retarding dopant segregation | Daniel Kadosh, Scott Luning, Akif Sultan | 2004-08-17 |
| 6743685 | Semiconductor device and method for lowering miller capacitance for high-speed microprocessors | Michael Duane, Scott Luning | 2004-06-01 |
| 6727136 | Formation of ultra-shallow depth source/drain extensions for MOS transistors | James F. Buller, Derick J. Wristers, Akif Sultan | 2004-04-27 |
| 6727558 | Channel isolation using dielectric isolation structures | Michael Duane, Massud Aminpur, Scott Luning | 2004-04-27 |
| 6624035 | Method of forming a hard mask for halo implants | Scott Luning, Massud Aminpur | 2003-09-23 |
| 6617219 | Semiconductor device and method for lowering miller capacitance by modifying source/drain extensions for high speed microprocessors | Michael Duane, Massud Aminpur, Scott Luning | 2003-09-09 |
| 6586311 | Salicide block for silicon-on-insulator (SOI) applications | — | 2003-07-01 |
| 6569606 | Method of reducing photoresist shadowing during angled implants | William R. Roche, Massud Aminpur, Scott Luning, Karen L. E. Turnqest | 2003-05-27 |
| 6482726 | Control trimming of hard mask for sub-100 nanometer transistor gate | Massud Aminpur, Scott Luning | 2002-11-19 |
| 6458678 | Transistor formed using a dual metal process for gate and source/drain region | Thomas E. Spikes, Jr., Frederick N. Hause | 2002-10-01 |
| 6391751 | Method for forming vertical profile of polysilicon gate electrodes | William R. Roche, Scott Luning, Karen L. E. Turnqest | 2002-05-21 |
| 6368926 | Method of forming a semiconductor device with source/drain regions having a deep vertical junction | — | 2002-04-09 |
| 6351013 | Low-K sub spacer pocket formation for gate capacitance reduction | Scott Luning, Khanh Tran | 2002-02-26 |
| 6277698 | Method of manufacturing semiconductor devices having uniform, fully doped gate electrodes | Emi Ishida, Dong-Hyuk Ju | 2001-08-21 |
| 6232208 | Semiconductor device and method of manufacturing a semiconductor device having an improved gate electrode profile | Dong-Hyuk Ju | 2001-05-15 |
| 6137137 | CMOS semiconductor device comprising graded N-LDD junctions with increased HCI lifetime | — | 2000-10-24 |
| 6114210 | Method of forming semiconductor device comprising a drain region with a graded N-LDD junction with increased HCI lifetime | Scott Luning | 2000-09-05 |
| 6107149 | CMOS semiconductor device comprising graded junctions with reduced junction capacitance | Scott Luning | 2000-08-22 |
| 5952693 | CMOS semiconductor device comprising graded junctions with reduced junction capacitance | Scott Luning | 1999-09-14 |
| 5925914 | Asymmetric S/D structure to improve transistor performance by reducing Miller capacitance | Chun Jiang | 1999-07-20 |