Issued Patents 2025
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12424515 | SOIC chip architecture | Chin-Chou Liu, Chin-Her Chien, Cheng-Hung Yeh, Hui Yu Lee, Po-Hsiang Huang +1 more | 2025-09-23 |
| 12423505 | Semiconductor device with cell region | Sheng-Hsiung Chen, Ho Che Yu | 2025-09-23 |
| 12412799 | Integrated circuit package and method | Chen-Hua Yu, Wei Ling Chang, Chuei-Tang Wang, Chieh-Yen Chen | 2025-09-09 |
| 12400989 | Arrangement of power-grounds in package structures | Ting-Yu Yeh, Chun Hua Chang, Jyh Chwen Frank Lee | 2025-08-26 |
| 12382724 | Layout design for header cell in 3D integrated circuits | Cheng-Yu Lin, Po-Hsiang Huang, Pochun Wang, Chih-Liang Chen | 2025-08-05 |
| 12368148 | Info packages including thermal dissipation blocks | Yu-Hao Chen, Po-Hsiang Huang, Ching-Yi Lin, Jyh Chwen Frank Lee | 2025-07-22 |
| 12321680 | Integrated circuit fin structure | Po-Hsiang Huang, Clement Hsingjen Wann, Chih-Hsin Ko, Sheng-Hsiung Chen, Li-Chun Tien +1 more | 2025-06-03 |
| 12315862 | Integrated circuit device with improved layout | Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao +2 more | 2025-05-27 |
| 12299369 | Systems and methods of estimating thermal properties of semiconductor devices | Ching-Yi Lin, Po-Yu Chen, Po-Hsiang Huang, Chih-Wei Chang, Jyh Chwen Frank Lee | 2025-05-13 |
| 12277379 | Method and system for generating layout diagram including wiring arrangement | Chin-Chou Liu, Hui-Zhong Zhuang, Meng-Kai Hsu, Pin-Dai Sue, Po-Hsiang Huang +3 more | 2025-04-15 |
| 12272658 | Method of making electrostatic discharge protection cell and antenna integrated with through silicon via | HoChe Yu, XinYong WANG, Chih-Liang Chen, Tzu-Heng Chang | 2025-04-08 |
| 12261095 | Semiconductor package having an encapulant comprising conductive fillers and method of manufacture | Xinyu BAO, Lee-Chung Lu, Jyh Chwen Frank Lee, Sam Vaziri, Po-Hsiang Huang | 2025-03-25 |
| 12224482 | Antenna effect protection and electrostatic discharge protection for three-dimensional integrated circuit | Po-Hsiang Huang, Tsui-Ping Wang, Yi-Shin Chu | 2025-02-11 |
| 12223252 | Through-silicon via in integrated circuit packaging | Chin-Chou Liu, Chin-Her Chien, Cheng-Hung Yeh, Po-Hsiang Huang, Sen-Bor Jan +2 more | 2025-02-11 |
| 12216981 | System and method for generating layout diagram including wiring arrangement | Chin-Chou Liu, Hui-Zhong Zhuang, Meng-Kai Hsu, Pin-Dai Sue, Po-Hsiang Huang +3 more | 2025-02-04 |
| 12190034 | Logic circuits with reduced transistor counts | Chi-Lin Liu, Jerry Chang Jui Kao, Wei-Hsiang Ma, Lee-Chung Lu, Sheng-Hsiung Chen +1 more | 2025-01-07 |