Issued Patents 2024
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12166026 | Semiconductor packages and methods for forming the same | Han-Tang Hung, Shin-Yi Yang, Shau-Lin Shue | 2024-12-10 |
| 12159814 | Semiconductor packages and methods for forming the same | Shin-Yi Yang, Shau-Lin Shue | 2024-12-03 |
| 12142557 | Integrated chip having a back-side power rail | Shin-Yi Yang, Shau-Lin Shue | 2024-11-12 |
| 12113021 | Graphene-assisted low-resistance interconnect structures and methods of formation thereof | Shin-Yi Yang, Yu-Chen Chan, Hai-Ching Chen, Shau-Lin Shue | 2024-10-08 |
| 12094848 | Semiconductor packages and methods for forming the same | Shin-Yi Yang, Shau-Lin Shue | 2024-09-17 |
| 12080593 | Barrier-less structures | Hsin-Ping Chen, Shin-Yi Yang, Yung-Hsu Wu, Chia-Tien Wu, Shau-Lin Shue +1 more | 2024-09-03 |
| 12080650 | Interconnect structure with low capacitance and high thermal conductivity | Kai-Fang Cheng, Hsiao-Kang Chang | 2024-09-03 |
| 12068254 | Interconnection structure and methods of forming the same | Shu-Wei Li, Yu-Chen Chan, Shin-Yi Yang, Shau-Lin Shue | 2024-08-20 |
| 12068253 | Semiconductor structure with two-dimensional conductive structures | Shu-Wei Li, Yu-Chen Chan, Meng-Pei Lu, Shin-Yi Yang | 2024-08-20 |
| 12062612 | Semiconductor device structure and methods of forming the same | Shu-Wei Li, Guanyu Luo, Shin-Yi Yang | 2024-08-13 |
| 12051683 | Semiconductor packages and methods for forming the same | Han-Tang Hung, Shin-Yi Yang, Shau-Lin Shue | 2024-07-30 |
| 12051645 | Two 2D capping layers on interconnect conductive structure to increase interconnect structure reliability | Shu-Wei Li, Yu-Chen Chan, Shin-Yi Yang | 2024-07-30 |
| 12051643 | Hybrid via interconnect structure | Chin-Lung Chung, Shin-Yi Yang | 2024-07-30 |
| 12027419 | Semiconductor device including liner structure | Ching-Fu Yeh, Yu-Chen Chan, Guanyu Luo, Meng-Pei Lu, Chao-Hsien Peng +2 more | 2024-07-02 |
| 11978663 | Integrated circuit interconnect structure having discontinuous barrier layer and air gap | Chin-Lung Chung, Shin-Yi Yang | 2024-05-07 |
| 11967552 | Methods of forming interconnect structures in semiconductor fabrication | Shau-Lin Shue | 2024-04-23 |
| 11948837 | Semiconductor structure having vertical conductive graphene and method for forming the same | Ching-Fu Yeh, Chin-Lung Chung, Shu-Wei Li, Yu-Chen Chan, Shin-Yi Yang | 2024-04-02 |
| 11929326 | Method of forming graphene barrier layer in interconnect structure | Shin-Yi Yang, Shau-Lin Shue | 2024-03-12 |
| 11908794 | Protection liner on interconnect wire to enlarge processing window for overlying interconnect via | Shin-Yi Yang, Hsin-Yen Huang, Shau-Lin Shue, Yu-Chen Chan, Meng-Pei Lu | 2024-02-20 |
| 11901349 | Semiconductor packages and methods for forming the same | Han-Tang Hung, Shin-Yi Yang, Shau-Lin Shue | 2024-02-13 |