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Tiered-profile contact for semiconductor |
Kangguo Cheng |
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| 12087691 |
Semiconductor structures with backside gate contacts |
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| 11990410 |
Top via interconnect having a line with a reduced bottom dimension |
Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert R. Robison |
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| 11990412 |
Buried power rails located in a base layer including first, second, and third etch stop layers |
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| 11972977 |
Fabrication of rigid close-pitch interconnects |
Chanro Park, Kenneth Chun Kuen Cheng, Koichi Motoyama |
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| 11961759 |
Interconnects having spacers for improved top via critical dimension and overlay tolerance |
Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert R. Robison |
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| 11915966 |
Backside power rail integration |
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| 11894265 |
Top via with damascene line and via |
Lawrence A. Clevenger, Brent A. Anderson, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert R. Robison |
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| 11869808 |
Top via process with damascene metal |
Lawrence A. Clevenger, Brent A. Anderson, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert R. Robison |
2024-01-09 |