Issued Patents 2024
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12156486 | Horizontal RRAM device and architecture for variability reduction | Timothy Mathew Philip, Christopher J. Penny, Youngseok Kim, Lawrence A. Clevenger | 2024-11-26 |
| 12148682 | Memory cell in wafer backside | Biswanath Senapati, Seiji Munetoh, Lawrence A. Clevenger, Geoffrey Burr, Kohji Hosokawa | 2024-11-19 |
| 12142525 | Self-aligning spacer tight pitch via | Lawrence A. Clevenger, Brent A. Anderson | 2024-11-12 |
| 12040373 | Liner-free resistance contacts and silicide with silicide stop layer | Nicolas Loubet, Christian Lavoie, Adra Carr | 2024-07-16 |
| 11990410 | Top via interconnect having a line with a reduced bottom dimension | Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Robert R. Robison | 2024-05-21 |
| 11961759 | Interconnects having spacers for improved top via critical dimension and overlay tolerance | Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Robert R. Robison | 2024-04-16 |
| 11908791 | Partial subtractive supervia enabling hyper-scaling | Sagarika Mukesh | 2024-02-20 |
| 11908738 | Interconnect including integrally formed capacitor | Chih-Chao Yang | 2024-02-20 |
| 11894265 | Top via with damascene line and via | Lawrence A. Clevenger, Brent A. Anderson, Kisik Choi, Christopher J. Penny, Robert R. Robison | 2024-02-06 |
| 11869783 | Optimizating semiconductor binning by feed-forward process adjustment | Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Theodorus E. Standaert, James H. Stathis | 2024-01-09 |
| 11869808 | Top via process with damascene metal | Lawrence A. Clevenger, Brent A. Anderson, Christopher J. Penny, Kisik Choi, Robert R. Robison | 2024-01-09 |