CY

Chih-Chao Yang

IBM: 27 patents #14 of 5,109Top 1%
TE Tessera: 1 patents #4 of 37Top 15%
📍 Glenmont, NY: #1 of 4 inventorsTop 25%
🗺 New York: #22 of 12,119 inventorsTop 1%
Overall (2024): #1,272 of 561,600Top 1%
28
Patents 2024

Issued Patents 2024

Showing 1–25 of 28 patents

Patent #TitleCo-InventorsDate
12183630 Additive interconnect formation Ashim Dutta, Ekmini Anuja De Silva, Jennifer Church 2024-12-31
12167700 Replacement bottom electrode structure for MRAM devices Oscar van der Straten, Koichi Motoyama, Joseph F. Maniscalco 2024-12-10
12144263 Stepped contact within memory region Ashim Dutta, Lili Cheng 2024-11-12
12133473 Contact structure formation for memory devices Ashim Dutta 2024-10-29
12120963 Contact structure formation for memory devices Lili Cheng, Ashim Dutta 2024-10-15
12108685 Multi-diameter magnetic random-access memory pillar structure Oscar van der Straten, Koichi Motoyama, Joseph F. Maniscalco 2024-10-01
12100653 Resistance tunable fuse structure formed by embedded thin metal layers Alexander Reznicek, Miaomiao Wang, Donald F. Canaperi 2024-09-24
12087624 Beol tip-to-tip shorting and time dependent dielectric breakdown Chanro Park, Koichi Motoyama, Kenneth Chun Kuen Cheng 2024-09-10
12062609 Electronic fuse structure embedded in top via Koichi Motoyama, Chanro Park, Hsueh-Chung Chen 2024-08-13
12057395 Top via interconnects without barrier metal between via and above line Koichi Motoyama, Kenneth Chun Kuen Cheng, Chanro Park 2024-08-06
12058942 MRAM cell embedded in a metal layer Ashim Dutta 2024-08-06
12027416 BEOL etch stop layer without capacitance penalty Chanro Park, Koichi Motoyama, Kenneth Chun Kuen Cheng 2024-07-02
12002498 Coaxial top MRAM electrode Oscar van der Straten, Koichi Motoyama 2024-06-04
12002758 Backside metal-insulator-metal (MIM) capacitors extending through backside interlayer dielectric (BILD) layer or semiconductor layer and partly through dielectric layer Ruilong Xie, Takeshi Nogami, Roy R. Yu, Balasubramanian Pranatharthiharan 2024-06-04
11990414 BEOL alternative metal interconnects: integration and process Theo Standaert 2024-05-21
11955152 Dielectric fill for tight pitch MRAM pillar array Ashim Dutta, Theodorus E. Standaert, Daniel C. Edelstein 2024-04-09
11942424 Via patterning for integrated circuits Tao Li, Ruilong Xie, Tsung-Sheng Kang 2024-03-26
11937435 High density two-tier MRAM structure Ashim Dutta 2024-03-19
11937514 High-density memory devices using oxide gap fill Theodorus E. Standaert, Daniel C. Edelstein 2024-03-19
11908888 Metal-insulator-metal capacitor structure supporting different voltage applications Baozhen Li, Nan Jing, Huimei Zhou 2024-02-20
11910722 Subtractive top via as a bottom electrode contact for an embedded memory Ashim Dutta 2024-02-20
11908738 Interconnect including integrally formed capacitor Nicholas Anthony Lanzillo 2024-02-20
11901224 Rework for metal interconnects using etch and thermal anneal Prasad Bhosale, Terry A. Spooner, Lawrence A. Clevenger 2024-02-13
11887641 Simultaneous electrodes for magneto-resistive random access memory devices Oscar van der Straten, Koichi Motoyama 2024-01-30
11881433 Advanced copper interconnects with hybrid microstructure Daniel C. Edelstein 2024-01-23