Issued Patents 2024
Showing 1–25 of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12183740 | Stacked field-effect transistors | Ruilong Xie, Curtis S. Durfee, Jay William Strane, Min Gyu Sung, Julien Frougier +1 more | 2024-12-31 |
| 12176345 | Stacked FET with independent gate control | Ruilong Xie, Julien Frougier, Juntao Li, Chanro Park | 2024-12-24 |
| 12176416 | Stacked nanosheet transistor with defect free channel | Lan Yu, Heng Wu, Chen Zhang | 2024-12-24 |
| 12166110 | Nanosheet channel-to-source and drain isolation | Marc A. Bergendahl, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan | 2024-12-10 |
| 12154971 | Forming nanosheet transistor using sacrificial spacer and inner spacers | Julien Frougier, Nicolas Loubet | 2024-11-26 |
| 12148663 | Tiered-profile contact for semiconductor | Kisik Choi | 2024-11-19 |
| 12150310 | Ferroelectric random-access memory cell | Julien Frougier, Ruilong Xie, Chanro Park, Min Gyu Sung | 2024-11-19 |
| 12136573 | Fabrication of a vertical fin field effect transistor with reduced dimensional variations | — | 2024-11-05 |
| 12136656 | Semiconductor structure having two-dimensional channel | Andrew Gaul, Julien Frougier, Ruilong Xie, Andrew M. Greene, Christopher J. Waskiewicz | 2024-11-05 |
| 12136655 | Backside electrical contacts to buried power rails | Ruilong Xie, Brent A. Anderson, Albert M. Young, Julien Frougier, Balasubramanian Pranatharthiharan +2 more | 2024-11-05 |
| 12132098 | Uniform interfacial layer on vertical fin sidewalls of vertical transport field-effect transistors | Shogo Mochizuki, Choonghyun Lee, Juntao Li | 2024-10-29 |
| 12119346 | Vertical field-effect transistor with wrap-around contact structure | Shogo Mochizuki, Juntao Li | 2024-10-15 |
| 12112782 | Compact MRAM architecture with magnetic bottom electrode | Julien Frougier, Karthik Yogendra, Dimitri Houssameddine, Ruilong Xie | 2024-10-08 |
| 12113067 | Forming N-type and P-type horizontal gate-all-around devices | Ruilong Xie, Juntao Li, Carl Radens | 2024-10-08 |
| 12107132 | Source/drain contact positioning under power rail | Ruilong Xie, Indira Seshadri, Eric R. Miller | 2024-10-01 |
| 12107147 | Self-aligned gate contact for VTFETs | Huimei Zhou, Su Chen Fan, Miaomiao Wang | 2024-10-01 |
| 12107014 | Nanosheet transistors with self-aligned gate cut | Julien Frougier, Huimei Zhou, Ruilong Xie, Chanro Park | 2024-10-01 |
| 12106969 | Substrate thinning for a backside power distribution network | Ruilong Xie, Balasubramanian Pranatharthiharan, Mukta G. Farooq, Julien Frougier, Takeshi Nogami +1 more | 2024-10-01 |
| 12094949 | Fin-type field effect transistor having a wrap-around gate with bottom isolation and inner spacers to reduce parasitic capacitance | Choonghyun Lee, Chanro Park, Ruilong Xie | 2024-09-17 |
| 12094972 | Gate-all-around field effect transistors having end portions of nanosheet channel layers adjacent to source/drain regions being wider than the center portions | Julien Frougier, Ruilong Xie, Chanro Park | 2024-09-17 |
| 12087691 | Semiconductor structures with backside gate contacts | Ruilong Xie, Julien Frougier, Veeraraghavan S. Basker, Lawrence A. Clevenger, Nicolas Loubet +3 more | 2024-09-10 |
| 12087770 | Complementary field effect transistor devices | Ruilong Xie, Julien Frougier, Heng Wu, Chen Zhang | 2024-09-10 |
| 12080714 | Buried local interconnect between complementary field-effect transistor cells | Ruilong Xie, Reinaldo Vega, Alexander Reznicek | 2024-09-03 |
| 12046643 | Semiconductor structures with power rail disposed under active gate | Julien Frougier, Ruilong Xie, Chanro Park | 2024-07-23 |
| 12027224 | Authenticity and yield by reading defective cells | Julien Frougier, Ruilong Xie | 2024-07-02 |