Issued Patents 2022
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11532547 | Interconnect structures with low-aspect-ratio contact vias | Cheng-Hsiung Tsai, Ming-Han Lee | 2022-12-20 |
| 11521896 | Selective deposition of a protective layer to reduce interconnect structure critical dimensions | Hsi-Wen Tien, Chih Wei Lu, Hsin-Chieh Yao, Yu-Teng Dai, Wei-Hao Liao | 2022-12-06 |
| 11495465 | Method and structure for semiconductor device having gate spacer protection layer | Chih Wei Lu, Hai-Ching Chen, Chien-Hua Huang, Tien-I Bao | 2022-11-08 |
| 11488926 | Self-aligned interconnect structure | Hsin-Chieh Yao, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai, Wei-Hao Liao | 2022-11-01 |
| 11482447 | Method of forming an integrated chip having a cavity between metal features | Hsi-Wen Tien, Chih Wei Lu, Hsin-Chieh Yao, Shau-Lin Shue, Yu-Teng Dai +1 more | 2022-10-25 |
| 11404367 | Method for forming semiconductor device with self-aligned conductive features | Tai-I Yang, Wei-Chen Chu, Yung-Hsu Wu | 2022-08-02 |
| 11393718 | Semiconductor structure and method for forming the same | Hwei-Jay CHU, Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu | 2022-07-19 |
| 11387113 | Method of fabricating semiconductor device with reduced trench distortions | Yung-Sung Yen, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen +4 more | 2022-07-12 |
| 11362030 | Sidewall spacer structure enclosing conductive wire sidewalls to increase reliability | Yu-Teng Dai, Chih Wei Lu, Hsin-Chieh Yao, Hsi-Wen Tien, Wei-Hao Liao | 2022-06-14 |
| 11355701 | Integrated circuit | Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Pin-Ren Dai | 2022-06-07 |
| 11329216 | Magnetic tunnel junction devices | Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu | 2022-05-10 |
| 11302641 | Self-aligned cavity strucutre | Wei-Hao Liao, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai | 2022-04-12 |
| 11251118 | Self-aligned via structures with barrier layers | Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu | 2022-02-15 |