Issued Patents 2022
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11532708 | Stacked three-dimensional field-effect transistors | Lars Liebmann, Daniel Chanemougame, Paul Gutwin | 2022-12-20 |
| 11495540 | Semiconductor apparatus having stacked devices and method of manufacture thereof | Lars Liebmann, Anton J. deVilliers | 2022-11-08 |
| 11488947 | Highly regular logic design for efficient 3D integration | Lars Liebmann, Daniel Chanemougame, Anton J. deVilliers | 2022-11-01 |
| 11450671 | Semiconductor apparatus having stacked devices and method of manufacture thereof | Lars Liebmann, Anton J. deVilliers, Daniel Chanemougame | 2022-09-20 |
| 11450562 | Method of bottom-up metallization in a recessed feature | Kai-Hung Yu, Jodi Grzeskowiak, Nicholas Joy | 2022-09-20 |
| 11444082 | Semiconductor apparatus having stacked gates and method of manufacture thereof | Anton J. deVilliers, Kandabara Tapily, Subhadeep Kal, Gerrit J. Leusink | 2022-09-13 |
| 11437376 | Compact 3D stacked-CFET architecture for complex logic cells | Lars Liebmann, Anton J. deVilliers, Daniel Chanemougame | 2022-09-06 |
| 11393694 | Method for planarization of organic films | Anton J. deVilliers, Robert Brandt, Jodi Grzeskowiak, Daniel Fulford | 2022-07-19 |
| 11360388 | Critical dimension correction via calibrated trim dosing | Anton J. deVilliers, Ronald Nasman | 2022-06-14 |
| 11335599 | Self-aligned contacts for 3D logic and memory | Lars Liebmann, Anton J. deVilliers, Kandabara Tapily | 2022-05-17 |
| 11322401 | Reverse contact and silicide process for three-dimensional semiconductor devices | Lars Liebmann, Daniel Chanemougame, Hiroki Niimi, Kandabara Tapily, Subhadeep Kal +2 more | 2022-05-03 |
| 11273855 | LED shielding and monitoring system and wayside LED signals | Axel Beier | 2022-03-15 |
| 11264274 | Reverse contact and silicide process for three-dimensional logic devices | Hiroaki Niimi, Jodi Grzeskowiak, Daniel Chanemougame, Lars Liebmann, Kandabara Tapily +2 more | 2022-03-01 |
| 11264289 | Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacks | Kandabara Tapily, Lars Liebmann, Daniel Chanemougame, Mark I. Gardner, H. Jim Fulford +1 more | 2022-03-01 |
| 11251200 | Coaxial contacts for 3D logic and memory | Lars Liebmann, Anton J. deVilliers, Kandabara Tapily | 2022-02-15 |
| 11217583 | Architecture design of monolithically integrated 3D CMOS logic and memory | Lars Liebmann, Anton J. deVilliers, Kandabara Tapily | 2022-01-04 |