Issued Patents 2022
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11532734 | Gate-all-around integrated circuit structures having germanium nanowire channel structures | Anand S. Murthy, Susmita Ghose, Zachary Geiger | 2022-12-20 |
| 11532706 | Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures | Anand S. Murthy, Susmita Ghose, Siddharth Chouksey | 2022-12-20 |
| 11522048 | Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs | Anand S. Murthy, Mark Bohr, Tahir Ghani, Biswajeet Guha | 2022-12-06 |
| 11521968 | Channel structures with sub-fin dopant diffusion blocking layers | Anand S. Murthy, Stephen M. Cea, Biswajeet Guha, Anupama Bowonder, Tahir Ghani | 2022-12-06 |
| 11482457 | Substrate defect blocking layers for strained channel semiconductor devices | Karthik Jambunathan, Anand S. Murthy | 2022-10-25 |
| 11450739 | Germanium-rich nanowire transistor with relaxed buffer layer | Glenn A. Glass, Anand S. Murthy, Tahir Ghani, Jack T. Kavalieros, Siddharth Chouksey +3 more | 2022-09-20 |
| 11430787 | Forming crystalline source/drain contacts on semiconductor devices | Karthik Jambunathan, Scott Maddox, Anand S. Murthy | 2022-08-30 |
| 11404575 | Diverse transistor channel materials enabled by thin, inverse-graded, germanium-based layer | Karthik Jambunathan, Glenn A. Glass, Anand S. Murthy, Ju H. Nam, Tahir Ghani | 2022-08-02 |
| 11374100 | Source or drain structures with contact etch stop layer | Rishabh Mehandru, Anupama Bowonder, Biswajeet Guha, Anand S. Murthy, Tahir Ghani | 2022-06-28 |
| 11328988 | Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication | Gilbert Dewey, Ryan Keech, Cheng-Ying Huang, Ashish Agrawal, Willy Rachmady +1 more | 2022-05-10 |
| 11264501 | Device, method and system for promoting channel stress in a NMOS transistor | Rishabh Mehandru, Anand S. Murthy, Karthik Jambunathan | 2022-03-01 |
| 11244943 | Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material | Cheng-Ying Huang, Gilbert Dewey, Ashish Agrawal, Kimin Jun, Willy Rachmady +5 more | 2022-02-08 |
| 11222977 | Source/drain diffusion barrier for germanium NMOS transistors | Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Tahir Ghani, Jack T. Kavalieros +3 more | 2022-01-11 |