Issued Patents 2022
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11532719 | Transistors on heterogeneous bonding layers | Jack T. Kavalieros, Gilbert Dewey, Willy Rachmady, Aaron D. Lilak, Brennen Mueller +5 more | 2022-12-20 |
| 11482621 | Vertically stacked CMOS with upfront M0 interconnect | Willy Rachmady, Patrick Morrow, Aaron D. Lilak, Rishabh Mehandru, Cheng-Ying Huang +4 more | 2022-10-25 |
| 11430814 | Metallization structures for stacked device connectivity and their methods of fabrication | Aaron D. Lilak, Anh Phan, Patrick Morrow, Willy Rachmady, Gilbert Dewey +6 more | 2022-08-30 |
| 11393777 | Microelectronic assemblies | Adel A. Elsherbini, Patrick Morrow, Henning Braunisch, Brennen Mueller, Shawna M. Liff +2 more | 2022-07-19 |
| 11393818 | Stacked transistors with Si PMOS and high mobility thin film transistor NMOS | Gilbert Dewey, Ravi Pillarisetty, Abhishek A. Sharma, Aaron D. Lilak, Willy Rachmady +5 more | 2022-07-19 |
| 11348897 | Microelectronic assemblies | Adel A. Elsherbini, Henning Braunisch, Aleksandar Aleksov, Shawna M. Liff, Johanna M. Swan +3 more | 2022-05-31 |
| 11264493 | Wrap-around source/drain method of making contacts for backside metals | Patrick Morrow, Il-Seok Son, Donald W. Nelson | 2022-03-01 |
| 11251156 | Fabrication and use of through silicon vias on double sided interconnect device | Brennen Mueller, Patrick Morrow, Paul B. Fischer, Daniel Pantuso | 2022-02-15 |
| 11251158 | Monolithic chip stacking using a die with double-sided interconnect layers | Anup Pancholi | 2022-02-15 |
| 11244943 | Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material | Cheng-Ying Huang, Gilbert Dewey, Ashish Agrawal, Willy Rachmady, Zachary Geiger +5 more | 2022-02-08 |