Issued Patents 2020
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10879375 | Gate tie-down enablement with inner spacer | Su Chen Fan, Andre P. Labonte, Lars Liebmann | 2020-12-29 |
| 10840354 | Approach to bottom dielectric isolation for vertical transport fin field effect transistors | Zhenxing Bi, Thamarai S. Devarajan, Balasubramanian Pranatharthiharan, Muthumanickam Sankarapandian | 2020-11-17 |
| 10784371 | Self aligned top extension formation for vertical transistors | Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek | 2020-09-22 |
| 10784258 | Selective contact etch for unmerged epitaxial source/drain regions | Alexander Reznicek | 2020-09-22 |
| 10707326 | Vertical field-effect-transistors having a silicon oxide layer with controlled thickness | Chi-Chun Liu, Luciana Meli, Muthumanickam Sankarapandian, Kristin Schmidt, Ankit Vora | 2020-07-07 |
| 10692985 | Protection of high-K dielectric during reliability anneal on nanosheet structures | Nicolas Loubet, Vijay Narayanan, Muthumanickam Sankarapandian | 2020-06-23 |
| 10651308 | Self aligned top extension formation for vertical transistors | Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek | 2020-05-12 |
| 10629702 | Approach to bottom dielectric isolation for vertical transport fin field effect transistors | Zhenxing Bi, Thamarai S. Devarajan, Balasubramanian Pranatharthiharan, Muthumanickam Sankarapandian | 2020-04-21 |
| 10580855 | High thermal budget compatible punch through stop integration using doped glass | Kangguo Cheng, Xin Miao, Chun-Chen Yeh | 2020-03-03 |
| 10580854 | High thermal budget compatible punch through stop integration using doped glass | Kangguo Cheng, Xin Miao, Chun-Chen Yeh | 2020-03-03 |
| 10529828 | Method of forming vertical transistor having dual bottom spacers | Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek | 2020-01-07 |