Issued Patents 2019
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10522633 | Methods and structures of novel contact feature | Wei-Hao Wu, Chia-Hao Chang, Jia-Chuan You, Yi-Hsiung Lin, Zhi-Chang Lin +2 more | 2019-12-31 |
| 10516051 | FinFET and method of fabrication thereof | Kuo-Cheng Ching, Kuan-Ting Pan, Ching-Wei Tsai, Ying-Keung Leung, Carlos H. Diaz | 2019-12-24 |
| 10516049 | Multi-gate device and method of fabrication thereof | Kuo-Cheng Ching, Ching-Wei Tsai, Carlos H. Diaz, Wai-Yi Lien, Ying-Keung Leung | 2019-12-24 |
| 10510856 | Semiconductor device and method | Ming-Ta Hsieh, Tetsu Ohtou, Ching-Wei Tsai | 2019-12-17 |
| 10510874 | Semiconductor device | Kuo-Cheng Ching, Kuan-Lun Cheng, Keng-Chu Lin, Shi Ning Ju | 2019-12-17 |
| 10510873 | Semiconductor device and manufacturing method thereof | Kuo-Cheng Ching, Shi Ning Ju, Kuan-Ting Pan, Kuan-Lun Cheng | 2019-12-17 |
| 10510860 | Semiconductor device and method of manufacturing the same | Chun-Hsiung Lin, Chia-Hao Chang, Wai-Yi Lien, Chih-Chao Chou, Pei-Yu Wang | 2019-12-17 |
| 10497792 | Contacts for highly scaled transistors | Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Jean-Pierre Colinge, Chun-Hsiung Lin +2 more | 2019-12-03 |
| 10497778 | Semiconductor device and manufacturing method thereof | Kuo-Cheng Ching, Ching-Wei Tsai, Kuan-Lun Cheng | 2019-12-03 |
| 10483367 | Vertical gate all around (VGAA) devices and methods of manufacturing the same | Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Chin-Chi Wang, Chi-Wen Liu +1 more | 2019-11-19 |
| 10483378 | Epitaxial features confined by dielectric fins and spacers | Kuo-Cheng Ching, Kuan-Lun Cheng | 2019-11-19 |
| 10468486 | SOI substrate, semiconductor device and method for manufacturing the same | Cheng-Ta Wu, Kuo-Hwa Tzeng, Yeur-Luen Tu, Chung-Yi Yu | 2019-11-05 |
| 10453522 | SRAM with stacked bit cells | Carlos H. Diaz, Jean-Pierre Colinge, Ta-Pen Guo | 2019-10-22 |
| 10431473 | FINFET with source/drain structure and method of fabrication thereof | Kuo-Cheng Ching, Ching-Wei Tsai, Ying-Keung Leung | 2019-10-01 |
| 10403714 | Fill fins for semiconductor devices | Kuo-Cheng Ching, Kuan-Lun Cheng | 2019-09-03 |
| 10403545 | Power reduction in finFET structures | Kuo-Cheng Ching, Kuan-Lun Cheng | 2019-09-03 |
| 10388771 | Method and device for forming cut-metal-gate feature | Zhi-Chang Lin, Wei-Hao Wu, Jia-Ni Yu, Huan-Chieh Su, Ting-Hung Hsu | 2019-08-20 |
| 10374058 | Semiconductor device and method for manufacturing the same | Huan-Chieh Su, Zhi-Chang Lin, Ting-Hung Hsu, Jia-Ni Yu, Wei-Hao Wu | 2019-08-06 |
| 10361280 | Gate structure for semiconductor device | Kuo-Cheng Ching, Ching-Wei Tsai, Kuan-Lun Cheng | 2019-07-23 |
| 10361220 | Method of forming FinFET channel and structures thereof | Ching-Wei Tsai, Kuo-Cheng Ching, Jhon Jhy Liaw, Wai-Yi Lien | 2019-07-23 |
| 10361126 | System and method for widening fin widths for small pitch FinFET devices | Kuo-Cheng Ching, Shi Ning Ju, Ying-Keung Leung, Carlos H. Diaz | 2019-07-23 |
| 10355137 | FINFETs with wrap-around silicide and method forming the same | Kuo-Cheng Ching, Ching-Wei Tsai, Chi-Wen Liu, Ying-Keung Leung | 2019-07-16 |
| 10347751 | Self-aligned epitaxy layer | Kuo-Cheng Ching, Kuan-Lun Cheng | 2019-07-09 |
| 10294101 | Semiconductor arrangement with one or more semiconductor columns | Jean-Pierre Colinge, Ta-Pen Guo, Carlos H. Diaz | 2019-05-21 |
| 10290635 | Buried interconnect conductor | Kuo-Cheng Ching, Shi Ning Ju, Kuan-Ting Pan, Kuan-Lun Cheng | 2019-05-14 |