Issued Patents 2019
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10510874 | Semiconductor device | Kuo-Cheng Ching, Chih-Hao Wang, Keng-Chu Lin, Shi Ning Ju | 2019-12-17 |
| 10510873 | Semiconductor device and manufacturing method thereof | Kuo-Cheng Ching, Shi Ning Ju, Kuan-Ting Pan, Chih-Hao Wang | 2019-12-17 |
| 10497778 | Semiconductor device and manufacturing method thereof | Kuo-Cheng Ching, Ching-Wei Tsai, Chih-Hao Wang | 2019-12-03 |
| 10483378 | Epitaxial features confined by dielectric fins and spacers | Kuo-Cheng Ching, Chih-Hao Wang | 2019-11-19 |
| 10403545 | Power reduction in finFET structures | Kuo-Cheng Ching, Chih-Hao Wang | 2019-09-03 |
| 10403714 | Fill fins for semiconductor devices | Kuo-Cheng Ching, Chih-Hao Wang | 2019-09-03 |
| 10361280 | Gate structure for semiconductor device | Kuo-Cheng Ching, Chih-Hao Wang, Ching-Wei Tsai | 2019-07-23 |
| 10347751 | Self-aligned epitaxy layer | Kuo-Cheng Ching, Chih-Hao Wang | 2019-07-09 |
| 10290635 | Buried interconnect conductor | Kuo-Cheng Ching, Shi Ning Ju, Kuan-Ting Pan, Chih-Hao Wang | 2019-05-14 |
| 10283623 | Integrated circuits with gate stacks | Li-Shyue Lai, Ching-Wei Tsai, Kai-Chieh Yang | 2019-05-07 |
| 10269914 | Semiconductor device and manufacturing method thereof | Wei-Hao Wu, Zhi-Chang Lin, Ting-Hung Hsu | 2019-04-23 |
| 10269803 | Hybrid scheme for improved performance for P-type and N-type FinFETs | Kuo-Cheng Ching, Shi Ning Ju, Ching-Wei Tsai, Chih-Hao Wang | 2019-04-23 |
| 10211307 | Methods of manufacturing inner spacers in a gate-all-around (GAA) FET through multi-layer spacer replacement | Kuo-Cheng Ching, Chih-Hao Wang, Ching-Wei Tsai | 2019-02-19 |