Issued Patents 2019
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10510744 | Vertical nanowire transistor for input/output structure | Jean-Pierre Colinge, Carlos H. Diaz | 2019-12-17 |
| 10453522 | SRAM with stacked bit cells | Carlos H. Diaz, Chih-Hao Wang, Jean-Pierre Colinge | 2019-10-22 |
| 10403550 | Method of manufacturing a semiconductor device and a semiconductor device | Hung-Li Chiang, Chao-Ching Cheng, Chih-Liang Chen, Tzu-Chiang Chen, Yu-Lin Yang +2 more | 2019-09-03 |
| 10325989 | Semiconductor device with silicide | Jean-Pierre Colinge, Kuo-Cheng Ching, Carlos H. Diaz | 2019-06-18 |
| 10312189 | Enhancing integrated circuit density with active atomic reservoir | Ming-Hsien Lin | 2019-06-04 |
| 10294101 | Semiconductor arrangement with one or more semiconductor columns | Jean-Pierre Colinge, Chih-Hao Wang, Carlos H. Diaz | 2019-05-21 |
| 10290737 | Semiconductor arrangement with one or more semiconductor columns | Jean-Pierre Colinge, Kuo-Cheng Ching, Carlos H. Diaz | 2019-05-14 |
| 10270430 | Cell of transmission gate free circuit and integrated circuit and integrated circuit layout including the same | Chi-Lin Liu, Shang-Chih Hsieh, Jerry Chang Jui Kao, Li-Chun Tien, Lee-Chung Lu | 2019-04-23 |
| 10191694 | 3D cross-bar nonvolatile memory | Jean-Pierre Colinge, Carlos H. Diaz | 2019-01-29 |
| 10170404 | Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure | Carlos H. Diaz, Jean-Pierre Colinge, Yi-Hsiung Lin | 2019-01-01 |