Issued Patents 2019
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10522694 | Methods of manufacturing semiconductor device | I-Sheng Chen, Szu-Wei Huang, Cheng-Hsien Wu, Chih Chieh Yeh | 2019-12-31 |
| 10522622 | Multi-gate semiconductor device and method for forming the same | Chao-Ching Cheng, I-Sheng Chen, Tzu-Chiang Chen, Shih-Syuan Huang | 2019-12-31 |
| 10438851 | Threshold voltage adjustment for a gate-all-around semiconductor structure | Szu-Wei Huang, Huan-Sheng Wei, Jon-Hsu Ho, Chih Chieh Yeh, Wen-Hsing Hsieh +2 more | 2019-10-08 |
| 10418363 | Replacement gate process for FinFET | Cheng-Yi Peng, Tsung-Yao Wen, Yee-Chia Yeo, Yen-Ming Chen | 2019-09-17 |
| 10403550 | Method of manufacturing a semiconductor device and a semiconductor device | Chao-Ching Cheng, Chih-Liang Chen, Tzu-Chiang Chen, Ta-Pen Guo, Yu-Lin Yang +2 more | 2019-09-03 |
| 10340366 | Semiconductor device and manufacturing method thereof | Cheng-Yi Peng, Chih Chieh Yeh, Chih-Sheng Chang, Hung-Ming Chen, Yee-Chia Yeo | 2019-07-02 |
| 10312369 | Semiconductor Fin FET device with epitaxial source/drain | Cheng-Yi Peng, Jyh-Cherng Sheu, Yee-Chia Yeo | 2019-06-04 |
| 10290550 | Strain enhancement for FinFETs | Tsung-Lin Lee, Chih Chieh Yeh, Feng Yuan, Wei-Jen Lai | 2019-05-14 |
| 10290548 | Semiconductor device structure with semiconductor wire | I-Sheng Chen, Tzu-Chiang Chen, Tung Ying Lee, Szu-Wei Huang, Huan-Sheng Wei | 2019-05-14 |
| 10290546 | Threshold voltage adjustment for a gate-all-around semiconductor structure | Szu-Wei Huang, Huan-Sheng Wei, Jon-Hsu Ho, Chih Chieh Yeh, Wen-Hsing Hsieh +2 more | 2019-05-14 |
| 10269800 | Vertical gate semiconductor device with steep subthreshold slope | Szu-Wei Huang, Chih Chieh Yeh, Yee-Chia Yeo | 2019-04-23 |