Issued Patents 2019
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10509883 | Method for layout generation with constrained hypergraph partitioning | Tsun-Yu Yang, Wei Hu, Jui-Feng Kuan, Hsien-Hsin Sean Lee, Po-Cheng Pan +2 more | 2019-12-17 |
| 10409943 | Efficient analog layout prototyping by layout reuse with routing preservation | Tung-Chieh Chen, Po-Cheng Pan, Ching-Yu Chin | 2019-09-10 |
| 10355108 | Method of forming a fin field effect transistor comprising two etching steps to define a fin structure | Feng Yuan, Tsung-Lin Lee, Chang-Yun Chang, Clement Hsingjen Wann | 2019-07-16 |
| 10340366 | Semiconductor device and manufacturing method thereof | Cheng-Yi Peng, Chih Chieh Yeh, Chih-Sheng Chang, Hung-Li Chiang, Yee-Chia Yeo | 2019-07-02 |