Issued Patents 2019
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10509883 | Method for layout generation with constrained hypergraph partitioning | Tsun-Yu Yang, Wei Hu, Jui-Feng Kuan, Hsien-Hsin Sean Lee, Hung-Wen Huang +2 more | 2019-12-17 |
| 10409943 | Efficient analog layout prototyping by layout reuse with routing preservation | Tung-Chieh Chen, Ching-Yu Chin, Hung-Ming Chen | 2019-09-10 |