Issued Patents 2019
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10509883 | Method for layout generation with constrained hypergraph partitioning | Tsun-Yu Yang, Jui-Feng Kuan, Hsien-Hsin Sean Lee, Po-Cheng Pan, Hung-Wen Huang +2 more | 2019-12-17 |
| 10169507 | Variation-aware circuit simulation | Chin-Cheng Kuo | 2019-01-01 |