Issued Patents 2019
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10509883 | Method for layout generation with constrained hypergraph partitioning | Tsun-Yu Yang, Wei Hu, Jui-Feng Kuan, Hsien-Hsin Sean Lee, Po-Cheng Pan +2 more | 2019-12-17 |
| 10229995 | Fabricating method of fin structure with tensile stress and complementary FinFET structure | Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He +4 more | 2019-03-12 |