Issued Patents 2019
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10515185 | Method of determining colorability of a semiconductor device and system for implementing the same | Chung-Yun Cheng, Chin-Chang Hsu, Jian-Yi Li, Li Ke, Wen-Ju Yang | 2019-12-24 |
| 10509883 | Method for layout generation with constrained hypergraph partitioning | Tsun-Yu Yang, Wei Hu, Jui-Feng Kuan, Po-Cheng Pan, Hung-Wen Huang +2 more | 2019-12-17 |
| 10489548 | Integrated circuit and method for manufacturing the same | Yu-Jung Chang, Chin-Chang Hsu, Wen-Ju Yang | 2019-11-26 |
| 10430334 | Memory circuit and cache circuit configuration | William Wu Shen, Yun-Han Lee | 2019-10-01 |
| 10430544 | Multi-patterning graph reduction and checking flow method | Nien-Yu Tsai, Chin-Chang Hsu, Wen-Ju Yang | 2019-10-01 |
| 10204205 | Method of determining colorability of a semiconductor device and system for implementing the same | Chung-Yun Cheng, Chin-Chang Hsu, Jian-Yi Li, Li Ke, Wen-Ju Yang | 2019-02-12 |