Issued Patents 2019
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10522409 | Fin field effect transistor (FinFET) device structure with dummy fin structure and method for forming the same | Tzung-Yi Tsai, Yen-Ming Chen, Tsung-Lin Lee | 2019-12-31 |
| 10522694 | Methods of manufacturing semiconductor device | I-Sheng Chen, Szu-Wei Huang, Hung-Li Chiang, Cheng-Hsien Wu | 2019-12-31 |
| 10522625 | Multi-gate device and method of fabrication thereof | I-Sheng Chen, Cheng-Hsien Wu, Yee-Chia Yeo | 2019-12-31 |
| 10516056 | Semiconductor device and manufacturing method thereof | I-Sheng Chen, Cheng-Hsien Wu | 2019-12-24 |
| 10504796 | Semiconductor device and method for manufacturing the same | I-Sheng Chen, Tzu-Chiang Chen, Cheng-Hsien Wu, Chih-Sheng Chang | 2019-12-10 |
| 10483157 | Semiconductor device and method of manufacturing the same | Meng-Hsuan Hsiao, Yee-Chia Yeo, Tung Ying Lee | 2019-11-19 |
| 10483262 | Dual nitride stressor for semiconductor device and method of manufacturing | Yu-Lin Yang, Chia-Cheng Ho, Cheng-Yi Peng, Tsung-Lin Lee | 2019-11-19 |
| 10438851 | Threshold voltage adjustment for a gate-all-around semiconductor structure | Hung-Li Chiang, Szu-Wei Huang, Huan-Sheng Wei, Jon-Hsu Ho, Wen-Hsing Hsieh +2 more | 2019-10-08 |
| 10374059 | Structure and formation method of semiconductor device structure with nanowires | Chao-Ching Cheng, Wei-Sheng Yun, Shao-Ming Yu, Tsung-Lin Lee | 2019-08-06 |
| 10355133 | Method for forming a semiconductor device including a stacked wire structure | Cheng-Hsien Wu, Yee-Chia Yeo | 2019-07-16 |
| 10340366 | Semiconductor device and manufacturing method thereof | Cheng-Yi Peng, Chih-Sheng Chang, Hung-Li Chiang, Hung-Ming Chen, Yee-Chia Yeo | 2019-07-02 |
| 10297508 | Semiconductor device and method | Chao-Ching Cheng, Tzu-Chiang Chen, Chen-Feng Hsu, Yu-Lin Yang, Tung Ying Lee | 2019-05-21 |
| 10290550 | Strain enhancement for FinFETs | Tsung-Lin Lee, Feng Yuan, Hung-Li Chiang, Wei-Jen Lai | 2019-05-14 |
| 10290546 | Threshold voltage adjustment for a gate-all-around semiconductor structure | Hung-Li Chiang, Szu-Wei Huang, Huan-Sheng Wei, Jon-Hsu Ho, Wen-Hsing Hsieh +2 more | 2019-05-14 |
| 10269800 | Vertical gate semiconductor device with steep subthreshold slope | Hung-Li Chiang, Szu-Wei Huang, Yee-Chia Yeo | 2019-04-23 |
| 10269934 | Method for manufacturing tunnel field effect transistor | I-Sheng Chen, Cheng-Hsien Wu | 2019-04-23 |
| 10263091 | Multiple gate field effect transistors having oxygen-scavenged gate stack | Yee-Chia Yeo, Chih-Hsin Ko, Cheng-Hsien Wu, Liang-Yin Chen, Xiong-Fei Yu +2 more | 2019-04-16 |
| 10204985 | Structure and formation method of semiconductor device structure | Tung Ying Lee, Chen-Feng Hsu | 2019-02-12 |
| 10181524 | Vertical transistor device and method for fabricating the same | Wei-Sheng Yun, Shao-Ming Yu | 2019-01-15 |
| 10170374 | Semiconductor device and method for manufacturing the same | I-Sheng Chen, Tzu-Chiang Chen, Cheng-Hsien Wu, Chih-Sheng Chang | 2019-01-01 |