Issued Patents 2017
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9847256 | Methods for forming a device having a capped through-substrate via structure | Yung-Chi Lin, Yen-Hung Chen, Yin Chen, Ebin Liao, Ku-Feng Yang +1 more | 2017-12-19 |
| 9842825 | Substrateless integrated circuit packages and methods of forming same | Lin-Chih Huang, Hung-An Teng, Hsin-Yu Chen, Cheng-Chieh Hsieh | 2017-12-12 |
| 9831177 | Through via structure | Yung-Chi Lin, Hsin-Yu Chen, Lin-Chih Huang, Wen-Chih Chiou | 2017-11-28 |
| 9786580 | Self-alignment for redistribution layer | Ku-Feng Yang, Ming-Tsu Chung, Hong-Ye Shih, Jiung Wu, Chen-Yu Tsai +2 more | 2017-10-10 |
| 9773701 | Methods of making integrated circuits including conductive structures through substrates | Yuan-Hung Liu, Ku-Feng Yang, Pei-Ching Kuo, Ming-Tsu Chung, Hsin-Yu Chen +1 more | 2017-09-26 |
| 9748190 | Low cost and ultra-thin chip on wafer on substrate (CoWoS) formation | Hsin-Yu Chen, Lin-Chih Huang, Tasi-Jung Wu, Wen-Chih Chiou | 2017-08-29 |
| 9679859 | Interconnect structure and method of forming same | Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin +2 more | 2017-06-13 |
| 9673132 | Interconnection structure with confinement layer | Hsiao Yun Lo, Yung-Chi Lin, Yang-Chih Hsueh, Wen-Chih Chiou | 2017-06-06 |