Issued Patents 2017
Showing 26–40 of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9660028 | Stacked transistors with different channel widths | Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian Pranatharthiharan | 2017-05-23 |
| 9658523 | Interconnect structure having large self-aligned vias | Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard S. Wise, Terry A. Spooner +1 more | 2017-05-23 |
| 9653585 | Vertical gate-all-around TFET | — | 2017-05-16 |
| 9646939 | Multilayer structure in an integrated circuit for damage prevention and detection and methods of creating the same | Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Byoung Youp Kim, Walter Kleemeier | 2017-05-09 |
| 9640483 | Via, trench or contact structure in the metallization, premetallization dielectric or interlevel dielectric layers of an integrated circuit | — | 2017-05-02 |
| 9640636 | Methods of forming replacement gate structures and bottom and top source/drain regions on a vertical transistor device | Steven Bentley, Kwan-Yong Lim, Hiroaki Niimi | 2017-05-02 |
| 9633986 | Technique for fabrication of microelectronic capacitors and resistors | Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Edem Wornyo | 2017-04-25 |
| 9607864 | Dual medium filter for ion and particle filtering during semiconductor processing | Laertis Economikos, Wei-Tsu Tseng, Adam Ticknor | 2017-03-28 |
| 9607893 | Method of forming self-aligned metal lines and vias | Carl Radens, Lawrence A. Clevenger | 2017-03-28 |
| 9601630 | Transistors incorporating metal quantum dots into doped source and drain regions | — | 2017-03-21 |
| 9570512 | High density resistive random access memory (RRAM) | Qing Liu | 2017-02-14 |
| 9548222 | Post-CMP hybrid wafer cleaning technique | — | 2017-01-17 |
| 9543304 | Vertical junction FinFET device and method for manufacture | Qing Liu | 2017-01-10 |
| 9543397 | Backside source-drain contact for integrated circuit transistor devices and method of making same | Walter Kleemeier | 2017-01-10 |
| 9536793 | Self-aligned gate-first VFETs using a gate spacer recess | Kwan-Yong Lim, Steven Bentley, Chanro Park | 2017-01-03 |