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USPTO Patent Rankings Data through Dec 31, 2025
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Stephen M. Cea — 9 Patents in 2017

Intel: 9 patents #205 of 5,604Top 4%
Hillsboro, OR: #15 of 457 inventorsTop 4%
Oregon: #164 of 4,319 inventorsTop 4%
Overall (2017): #8,328 of 506,227Top 2%
9 Patents 2017

Issued Patents 2017

Showing 1–9 of 9 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
9711598 Two-dimensional condensation for uniaxially strained semiconductor fins Jack T. Kavalieros, Nancy Zelick, Been-Yih Jin, Markus Kuhn 2017-07-18 $6,909,000
9680013 Non-planar device having uniaxially strained semiconductor body and method of making same Roza Kotlyar, Jack T. Kavalieros, Martin D. Giles, Tahir Ghani, Kelin J. Kuhn +2 more 2017-06-13 $8,497,000
9673302 Conversion of strain-inducing buffer to electrical insulator Annalisa Cappellani, Van H. Le, Glenn A. Glass, Kelin J. Kuhn 2017-06-06 $12,588,000
9608059 Semiconductor device with isolated body portion Annalisa Cappellani, Tahir Ghani, Harry Gomez, Jack T. Kavalieros, Patrick H. Keys +5 more 2017-03-28 $8,391,000
9595581 Silicon and silicon germanium nanowire structures Kelin J. Kuhn, Seiyon Kim, Rafael Rios, Martin D. Giles, Annalisa Cappellani +3 more 2017-03-14 $10,939,000
9583602 Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs Roza Kotlyar, Gilbert Dewey, Benjamin Chu-Kung, Uygar E. Avci, Rafael Rios +4 more 2017-02-28 $9,011,000
9583491 CMOS nanowire structure Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Annalisa Cappellani +2 more 2017-02-28 $9,011,000
9570614 Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation Ravi Pillarisetty, Sansaptak Dasgupta, Niti Goel, Van H. Le, Marko Radosavljevic +8 more 2017-02-14 $9,787,000
9564522 Nanowire structures having non-discrete source and drain regions Annalisa Cappellani, Martin D. Giles, Rafael Rios, Seiyon Kim, Kelin J. Kuhn 2017-02-07 $9,424,000