Issued Patents 2017
Showing 26–50 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9685555 | High-reliability, low-resistance contacts for nanoscale transistors | Qing Liu, Nicolas Loubet, Ruilong Xie, Xiuyu Cai | 2017-06-20 |
| 9680020 | Increased contact area for FinFETs | Veeraraghavan S. Basker, Chung-Hsun Lin, Zuoguang Liu, Tenko Yamashita | 2017-06-13 |
| 9666726 | Localized fin width scaling using a hydrogen anneal | Veeraraghavan S. Basker, Shogo Mochizuki, Tenko Yamashita | 2017-05-30 |
| 9660083 | LDMOS finFET device and method of manufacture using a trench confined epitaxial growth process | Qing Liu, Ruilong Xie, Xiuyu Cai | 2017-05-23 |
| 9660035 | Semiconductor device including superlattice SiGe/Si fin structure | Veeraraghavan S. Basker, Tenko Yamashita | 2017-05-23 |
| 9660077 | Stress memorization technique for strain coupling enhancement in bulk finFET device | Kangguo Cheng, Juntao Li | 2017-05-23 |
| 9660057 | Method of forming a reduced resistance fin structure | Qing Liu, Ruilong Xie, Xiuyu Cai, Kejia Wang | 2017-05-23 |
| 9653579 | Method for making semiconductor device with filled gate line end recesses | Qing Liu, Ruilong Xie, Xiuyu Cai, Kejia Wang | 2017-05-16 |
| 9646962 | Low leakage gate controlled vertical electrostatic discharge protection device integration with a planar FinFET | Qing Liu, Ruilong Xie | 2017-05-09 |
| 9640633 | Self aligned gate shape preventing void formation | Andrew M. Greene, Qing Liu, Ruilong Xie | 2017-05-02 |
| 9634117 | Self-aligned contact process enabled by low temperature | Hong He, Chiahsun Tseng, Yunpeng Yin | 2017-04-25 |
| 9634000 | Partially isolated fin-shaped field effect transistors | Hong He, Chiahsun Tseng, Yunpeng Yin | 2017-04-25 |
| 9620505 | Semiconductor device with different fin sets | Qing Liu, Xiuyu Cai, Ruilong Xie, Kejia Wang, Daniel Chanemougame | 2017-04-11 |
| 9620644 | Composite spacer enabling uniform doping in recessed fin devices | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2017-04-11 |
| 9607900 | Method and structure to fabricate closely packed hybrid nanowires at scaled pitch | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2017-03-28 |
| 9608069 | Self aligned epitaxial based punch through control | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2017-03-28 |
| 9601621 | Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded SiGe source/drain | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2017-03-21 |
| 9595597 | Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded SiGe source/drain | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2017-03-14 |
| 9583585 | Gate structure integration scheme for fin field effect transistors | Hong He, Chiahsun Tseng, Yunpeng Yin | 2017-02-28 |
| 9577096 | Salicide formation on replacement metal gate finFet devices | Effendi Leobandung, Soon-Cheon Seo, Tenko Yamashita | 2017-02-21 |
| 9570466 | Structure and method to form passive devices in ETSOI process flow | Ming Cai, Dechao Guo | 2017-02-14 |
| 9564501 | Reduced trench profile for a gate | Qing Liu, Xiuyu Cai, Ruilong Xie | 2017-02-07 |
| 9564372 | Dual liner silicide | Balasubramanian Pranatharthiharan, Ruilong Xie | 2017-02-07 |
| 9559191 | Punch through stopper in bulk finFET device | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2017-01-31 |
| 9559018 | Dual channel finFET with relaxed pFET region | Xiuyu Cai, Qing Liu, Ruilong Xie | 2017-01-31 |