| 9520357 |
Anti-fuse structure and method for manufacturing the same |
Hong He, Juntao Li, Junli Wang |
2016-12-13 |
| 9514981 |
Interconnect structure |
Dinesh A. Badami, Baozhen Li, Wen Liu |
2016-12-06 |
| 9496239 |
Nitride-enriched oxide-to-oxide 3D wafer bonding |
Daniel C. Edelstein |
2016-11-15 |
| 9484254 |
Size-filtered multimetal structures |
David V. Horak, Charles W. Koburger, III, Shom Ponoth |
2016-11-01 |
| 9484201 |
Epitaxial silicon germanium fin formation using sacrificial silicon fin templates |
Hong He, Juntao Li, Junli Wang |
2016-11-01 |
| 9455350 |
Transistor device structure that includes polycrystalline semiconductor thin film that has large grain size |
Jia-Min Shieh, Wen-Hsien Huang, Chang-Hong Shen, Tung-Ying Hsieh |
2016-09-27 |
| 9437714 |
Selective gate contact fill metallization |
Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten |
2016-09-06 |
| 9406617 |
Structure and process for W contacts |
Daniel C. Edelstein, Baozhen Li |
2016-08-02 |
| 9392690 |
Method and structure to improve the conductivity of narrow copper filled vias |
Fenton R. McFeely |
2016-07-12 |
| 9385025 |
E-fuses containing at least one underlying tungsten contact for programming |
Rajiv V. Joshi |
2016-07-05 |
| 9379198 |
Integrated circuit structure having selectively formed metal cap |
David V. Horak, Charles W. Koburger, III, Shom Ponoth |
2016-06-28 |
| 9379221 |
Bottom-up metal gate formation on replacement metal gate finFET devices |
Hong He, Juntao Li, Junli Wang |
2016-06-28 |
| 9349691 |
Semiconductor device with reduced via resistance |
Conal E. Murray |
2016-05-24 |
| 9343407 |
Method to fabricate copper wiring structures and structures formed thereby |
Fenton R. McFeely |
2016-05-17 |
| 9331073 |
Epitaxially grown quantum well finFETs for enhanced pFET performance |
Marc A. Bergendahl, James J. Demarest, Hong He, Seth L. Knupp, Raghavasimhan Sreenivasan +2 more |
2016-05-03 |
| 9312203 |
Dual damascene structure with liner |
Baozhen Li |
2016-04-12 |
| 9281211 |
Nanoscale interconnect structure |
Stephan A. Cohen, Eric G. Liniger |
2016-03-08 |
| 9281305 |
Transistor device structure |
Jia-Min Shieh, Wen-Hsien Huang, Tung-Ying Hsieh, Chang-Hong Shen, Szu-Hung Chen |
2016-03-08 |
| 9276013 |
Integrated formation of Si and SiGe fins |
Bruce B. Doris, Hong He, Juntao Li, Junli Wang |
2016-03-01 |
| 9269621 |
Dual damascene dual alignment interconnect scheme |
Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Shom Ponoth |
2016-02-23 |
| 9263290 |
Sub-lithographic semiconductor structures with non-constant pitch |
Marc A. Bergendahl, David V. Horak, Charles W. Koburger, III, Shom Ponoth |
2016-02-16 |
| 9263388 |
Overlay-tolerant via mask and reactive ion etch (RIE) technique |
Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Shom Ponoth |
2016-02-16 |
| 9245794 |
Formation of alloy liner by reaction of diffusion barrier and seed layer for interconnect application |
Daniel C. Edelstein, Takeshi Nogami |
2016-01-26 |
