Issued Patents 2011
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8058123 | Integrated circuit and method of fabrication thereof | Jinping Liu, Hai Cong, Binbin Zhou, Alex See, Mei Sheng Zhou | 2011-11-15 |
| 8057968 | Mask and method to pattern chromeless phase lithography contact hole | Sia Kim Tan, Soon Yoeng Tan, Qun Ying Lin, Huey Ming Chong | 2011-11-15 |
| 8048588 | Method and apparatus for removing radiation side lobes | Sia Kim Tan, Soon Yoeng Tan, Qunying Lin, Huey Ming Chong | 2011-11-01 |
| 8012839 | Method for fabricating a semiconductor device having an epitaxial channel and transistor having same | Jinping Liu, Alex See, Mei Sheng Zhou | 2011-09-06 |
| 7999325 | Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS | Young Way Teh, Yong Meng Lee, Chung Woh Lai, Wenhe Lin, Khee Yong Lim +3 more | 2011-08-16 |
| 7989338 | Grain boundary blocking for stress migration and electromigration improvement in CU interconnects | Fan Zhang, Kho Liep Chok, Alex See, Cheng Tan, Xiaomei Bu +1 more | 2011-08-02 |
| 7960283 | Method for reducing silicide defects in integrated circuits | Jeff Jianhui Ye, Huang Liu, Alex See, Wei Lu, Hai Cong +2 more | 2011-06-14 |
| 7960282 | Method of manufacture an integrated circuit system with through silicon via | Pradeep Ramachandramurthy Yelehanka, Denise Tan, Chung Meng Lek, Thomas Thiam, Jeffrey Lam | 2011-06-14 |
| 7928020 | Method of fabricating a nitrogenated silicon oxide layer and MOS device having same | Jinping Liu, Ben Ong, Zhengquan Zhang, Jae Gon Lee, Lydia Wong +3 more | 2011-04-19 |