Issued Patents 2011
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8053327 | Method of manufacture of an integrated circuit system with self-aligned isolation structures | Shailendra Mishra, Lee-Wee Teo, Yong Meng Lee, Zhao Lun, Shyue Seng Tan +2 more | 2011-11-08 |
| 7999300 | Memory cell structure and method for fabrication thereof | Zhao Lun, James Yong Meng Lee, Lee-Wee Teo, Shyue Seng Tan, Johnny Widodo +2 more | 2011-08-16 |
| 7999325 | Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS | Young Way Teh, Yong Meng Lee, Wenhe Lin, Khee Yong Lim, Wee Leng Tan +3 more | 2011-08-16 |
| 7977185 | Method and apparatus for post silicide spacer removal | Brian J. Greene, Yong Meng Lee, Wenhe Lin, Siddhartha Panda, Kern Rim +1 more | 2011-07-12 |
| 7955936 | Semiconductor fabrication process including an SiGe rework method | Yong Siang Tan, Jin-Ping Han, Henry K. Utomo, Judson R. Holt, Eric C. Harley +2 more | 2011-06-07 |
| 7935593 | Stress optimization in dual embedded epitaxially grown semiconductor processing | Jong-ho Yang, Jin-Ping Han, Henry K. Utomo | 2011-05-03 |
| 7932178 | Integrated circuit having a plurality of MOSFET devices | Lee-Wee Teo, Yong Meng Lee, Jeffrey Chee, Shyue Seng Tan, Johnny Widodo +2 more | 2011-04-26 |