Issued Patents 2004
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6828205 | Method using wet etching to trim a critical dimension | Ming-Huan Tsai, Ming-Jie Huang, Huan-Just Lin | 2004-12-07 |
| 6828248 | Method of pull back for forming shallow trench isolation | Huan-Just Lin | 2004-12-07 |
| 6821880 | Process of dual or single damascene utilizing separate etching and DCM apparati | Chao-Cheng Chen | 2004-11-23 |
| 6812044 | Advanced control for plasma process | Hsien-Kuang Chiu, Bor-Wen Chan, Baw-Ching Perng, Yuan-Hung Chiu | 2004-11-02 |
| 6794302 | Dynamic feed forward temperature control to achieve CD etching uniformity | Li-Shiun Chen, Ming-Ching Chang, Huan-Just Lin, Li-Te Lin, Yung-Hog Chiu | 2004-09-21 |
| 6794230 | Approach to improve line end shortening | Ming-Jie Huang | 2004-09-21 |
| 6787455 | Bi-layer photoresist method for forming high resolution semiconductor features | Ming-Huan Tsai, Ju-Wang Hsu, Cheng-Ku Chen | 2004-09-07 |
| 6780782 | Bi-level resist structure and fabrication method for contact holes on semiconductor substrates | Ming-Huan Tsai, Tsang-Jiuh Wu, Ju-Wang Hsu | 2004-08-24 |
| 6777340 | Method of etching a silicon containing layer using multilayer masks | Hsien-Kuang Chiu, Fang Chen, Yuan-Hung Chiu, Jeng-Horng Chen | 2004-08-17 |
| 6764911 | Multiple etch method for fabricating spacer layers | Jw-Wang Hsu, Ming-Huan Tsai, Mei-Ru Kuo, Baw-Ching Peng | 2004-07-20 |
| 6764903 | Dual hard mask layer patterning method | Bor-Wen Chan, Yuan-Hung Chiu | 2004-07-20 |
| 6720132 | Bi-layer photoresist dry development and reactive ion etch method | Ming-Huan Tsai | 2004-04-13 |
| 6706640 | Metal silicide etch resistant plasma etch method | Ming-Huan Tsai, Ju-Wang Hsu, Peng-Fu Hsu | 2004-03-16 |
| 6706591 | Method of forming a stacked capacitor structure with increased surface area for a DRAM device | Bor-Wen Chan, Huan-Just Lin | 2004-03-16 |
| 6686129 | Partial photoresist etching | Ming-Ching Chang | 2004-02-03 |