Issued Patents 2002
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6501120 | Capacitor under bitline (CUB) memory cell structure employing air gap void isolation | Yeur-Luen Tu, Min-hwa Chi | 2002-12-31 |
| 6497993 | In situ dry etching procedure to form a borderless contact hole | Yuan-Hunh Chiu, Hun-Jan Tao, Chu-Yun Fu | 2002-12-24 |
| 6491042 | Post etching treatment process for high density oxide etcher | Bao-Ru Young | 2002-12-10 |
| 6486025 | Methods for forming memory cell structures | Yuan-Hung Liu, Yeur-Luen Tu, Min-hwa Chi, Chih-Hsing Yu | 2002-11-26 |
| 6486529 | Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications | Min-hwa Chi, Yeur-Luen Tu | 2002-11-26 |
| 6472335 | Methods of adhesion promoter between low-K layer and underlying insulating layer | Yao-Yi Cheng, Hun-Jan Tao | 2002-10-29 |
| 6429119 | Dual damascene process to reduce etch barrier thickness | Li-Chih Chao, Ming-Huei Lui, Jen-Cheng Liu, Chao-Cheng Chen | 2002-08-06 |
| 6417569 | Fluorine-doped silicate glass hard mask to improve metal line etching profile | Shau-Lin Shue | 2002-07-09 |
| 6399515 | Plasma etch method for forming patterned chlorine containing plasma etchable silicon containing layer with enhanced sidewall profile uniformity | Hun-Jan Tao | 2002-06-04 |
| 6399483 | Method for improving faceting effect in dual damascene process | Jen-Cheng Liu, Ming-Huei Lui, Hun-Jan Tao | 2002-06-04 |
| 6383943 | Process for improving copper fill integrity | Chao-Cheng Chen, Jen-Cheng Liu, Jyu-Horng Shieh, Bor-Shyang Lin | 2002-05-07 |
| 6362012 | Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications | Min-hwa Chi, Yeur-Luen Tu | 2002-03-26 |