Issued Patents 2002
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6468853 | Method of fabricating a shallow trench isolation structure with reduced local oxide recess near corner | Palanivel Balasubramanian, Chivkula Subrahmanyam, Narayanan Balasubramanian | 2002-10-22 |
| 6468877 | Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner | Jia Zhen Zheng, Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan +2 more | 2002-10-22 |
| 6461887 | Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growth | Jia Zhen Zheng, Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan +2 more | 2002-10-08 |
| 6461900 | Method to form a self-aligned CMOS inverter using vertical device integration | Ravi Sundaresan, Yang Pan, James Lee Yong Meng, Ying-Keung Leung, Jia Zhen Zheng +2 more | 2002-10-08 |
| 6455377 | Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs) | Jia Zhen Zheng, Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan +2 more | 2002-09-24 |
| 6451704 | Method for forming PLDD structure with minimized lateral dopant diffusion | Subrahmanyam Chivukula, Jie Ye, Madhudsudan Mukhopdhyay | 2002-09-17 |
| 6440800 | Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers | James Yong Meng Lee, Ying-Keung Leung, Jia Zhen Zheng, Lap Chan, Elgin Quek +2 more | 2002-08-27 |
| 6436774 | Method for forming variable-K gate dielectric | James Yong Meng Lee, Ying-Keung Leung, Jia Zhen Zheng, Lap Chan, Elgin Quek +2 more | 2002-08-20 |
| 6436770 | Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation | Ying-Keung Leung, Jia Zhen Zheng, Lap Chan, Elgin Quek, Ravi Sundaresan +2 more | 2002-08-20 |
| 6417056 | Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge | Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying-Keung Leung +2 more | 2002-07-09 |
| 6417054 | Method for fabricating a self aligned S/D CMOS device on insulated layer by forming a trench along the STI and fill with oxide | Jia Zhen Zheng, Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan +2 more | 2002-07-09 |
| 6406945 | Method for forming a transistor gate dielectric with high-K and low-K regions | James Yong Meng Lee, Ying-Keung Leung, Jia Zhen Zheng, Lap Chan, Elgin Quek +2 more | 2002-06-18 |
| 6403485 | Method to form a low parasitic capacitance pseudo-SOI CMOS device | Elgin Quek, Ravi Sundaresan, Yang Pan, James Lee Yong Meng, Ying Keung +2 more | 2002-06-11 |
| 6399448 | Method for forming dual gate oxide | Madhusudan Mukhopadhyay, Chivukula Subrahmanyam | 2002-06-04 |
| 6387765 | Method for forming an extended metal gate using a damascene process | Vijai Kumar Chhagan, Mei Sheng Zhou, Henry Gerung, Simon Chooi | 2002-05-14 |
| 6380088 | Method to form a recessed source drain on a trench side wall with a replacement gate technique | Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee +2 more | 2002-04-30 |
| 6355581 | Gas-phase additives for an enhancement of lateral etch component during high density plasma film deposition to improve film gap-fill capability | Vladislav Vassiliev, John Sudijono, Jie Yu | 2002-03-12 |
| 6346468 | Method for forming an L-shaped spacer using a disposable polysilicon spacer | Subhash Gupta, Vijai Chhagan | 2002-02-12 |
| 6337262 | Self aligned T-top gate process integration | Chivukula Subrahmanyam, Vijai Kumar Chhagan, Henry Gerung | 2002-01-08 |